Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  linux/arch/arm/mach-pxa/irq.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Generic PXA IRQ handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  Author:	Nicolas Pitre
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *  Created:	Jun 15, 2001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *  Copyright:	MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/exception.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <mach/irqs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include "generic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define ICIP			(0x000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define ICMR			(0x004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define ICLR			(0x008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define ICFR			(0x00c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define ICPR			(0x010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define ICCR			(0x014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define ICHP			(0x018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define IPR(i)			(((i) < 32) ? (0x01c + ((i) << 2)) :		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 				((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) :	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 				      (0x144 + (((i) - 64) << 2)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define ICHP_VAL_IRQ		(1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define ICHP_IRQ(i)		(((i) >> 16) & 0x7fff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define IPR_VALID		(1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define MAX_INTERNAL_IRQS	128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  * This is for peripheral IRQs internal to the PXA chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static void __iomem *pxa_irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static int pxa_internal_irq_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static bool cpu_has_ipr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static struct irq_domain *pxa_irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static inline void __iomem *irq_base(int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	static unsigned long phys_base_offset[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		0x9c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		0x130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	return pxa_irq_base + phys_base_offset[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) void pxa_mask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	void __iomem *base = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	irq_hw_number_t irq = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	uint32_t icmr = __raw_readl(base + ICMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	icmr &= ~BIT(irq & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	__raw_writel(icmr, base + ICMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) void pxa_unmask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	void __iomem *base = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	irq_hw_number_t irq = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	uint32_t icmr = __raw_readl(base + ICMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	icmr |= BIT(irq & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	__raw_writel(icmr, base + ICMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static struct irq_chip pxa_internal_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	.name		= "SC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	.irq_ack	= pxa_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	.irq_mask	= pxa_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	.irq_unmask	= pxa_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	uint32_t icip, icmr, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		icip = __raw_readl(pxa_irq_base + ICIP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		icmr = __raw_readl(pxa_irq_base + ICMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		mask = icip & icmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		if (mask == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		handle_IRQ(PXA_IRQ(fls(mask) - 1), regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	} while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	uint32_t ichp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		__asm__ __volatile__("mrc p6, 0, %0, c5, c0, 0\n": "=r"(ichp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		if ((ichp & ICHP_VAL_IRQ) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		handle_IRQ(PXA_IRQ(ICHP_IRQ(ichp)), regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	} while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int pxa_irq_map(struct irq_domain *h, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		       irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	void __iomem *base = irq_base(hw / 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	/* initialize interrupt priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	if (cpu_has_ipr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		__raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	irq_set_chip_and_handler(virq, &pxa_internal_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 				 handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	irq_set_chip_data(virq, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static const struct irq_domain_ops pxa_irq_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	.map    = pxa_irq_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.xlate  = irq_domain_xlate_onecell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static __init void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) pxa_init_irq_common(struct device_node *node, int irq_nr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		    int (*fn)(struct irq_data *, unsigned int))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	pxa_internal_irq_nr = irq_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	pxa_irq_domain = irq_domain_add_legacy(node, irq_nr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 					       PXA_IRQ(0), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 					       &pxa_irq_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	if (!pxa_irq_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		panic("Unable to add PXA IRQ domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	irq_set_default_host(pxa_irq_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	for (n = 0; n < irq_nr; n += 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		void __iomem *base = irq_base(n >> 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		__raw_writel(0, base + ICMR);	/* disable all IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		__raw_writel(0, base + ICLR);	/* all IRQs are IRQ, not FIQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	/* only unmasked interrupts kick us out of idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	__raw_writel(1, irq_base(0) + ICCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	pxa_internal_irq_chip.irq_set_wake = fn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	BUG_ON(irq_nr > MAX_INTERNAL_IRQS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	pxa_irq_base = io_p2v(0x40d00000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	cpu_has_ipr = !cpu_is_pxa25x();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	pxa_init_irq_common(NULL, irq_nr, fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static unsigned long saved_ipr[MAX_INTERNAL_IRQS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int pxa_irq_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	for (i = 0; i < DIV_ROUND_UP(pxa_internal_irq_nr, 32); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		void __iomem *base = irq_base(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		saved_icmr[i] = __raw_readl(base + ICMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		__raw_writel(0, base + ICMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	if (cpu_has_ipr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		for (i = 0; i < pxa_internal_irq_nr; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			saved_ipr[i] = __raw_readl(pxa_irq_base + IPR(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static void pxa_irq_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	for (i = 0; i < DIV_ROUND_UP(pxa_internal_irq_nr, 32); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		void __iomem *base = irq_base(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		__raw_writel(saved_icmr[i], base + ICMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		__raw_writel(0, base + ICLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (cpu_has_ipr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		for (i = 0; i < pxa_internal_irq_nr; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			__raw_writel(saved_ipr[i], pxa_irq_base + IPR(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	__raw_writel(1, pxa_irq_base + ICCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define pxa_irq_suspend		NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define pxa_irq_resume		NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct syscore_ops pxa_irq_syscore_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	.suspend	= pxa_irq_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	.resume		= pxa_irq_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const struct of_device_id intc_ids[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	{ .compatible = "marvell,pxa-intc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	node = of_find_matching_node(NULL, intc_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	if (!node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		pr_err("Failed to find interrupt controller in arch-pxa\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	ret = of_property_read_u32(node, "marvell,intc-nr-irqs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 				   &pxa_internal_irq_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		pr_err("Not found marvell,intc-nr-irqs property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	ret = of_address_to_resource(node, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		pr_err("No registers defined for node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	pxa_irq_base = io_p2v(res.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	if (of_find_property(node, "marvell,intc-priority", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		cpu_has_ipr = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	ret = irq_alloc_descs(-1, 0, pxa_internal_irq_nr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		pr_err("Failed to allocate IRQ numbers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	pxa_init_irq_common(node, pxa_internal_irq_nr, fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #endif /* CONFIG_OF */