^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * arch/arm/mach-pxa/include/mach/idp.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2001 Cliff Brake, Accelent Systems Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * 2001-09-13: Cliff Brake <cbrake@accelent.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Initial code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * 2005-02-15: Cliff Brake <cliff.brake@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * <http://www.vibren.com> <http://bec-systems.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Changes for 2.6 kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Note: this file must be safe to include in assembly files
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Support for the Vibren PXA255 IDP requires rev04 or later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * IDP hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <mach/irqs.h> /* PXA_GPIO_TO_IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IDP_FLASH_PHYS (PXA_CS0_PHYS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IDP_ALT_FLASH_PHYS (PXA_CS1_PHYS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IDP_MEDIAQ_PHYS (PXA_CS3_PHYS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IDP_IDE_PHYS (PXA_CS5_PHYS + 0x03000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IDP_ETH_PHYS (PXA_CS5_PHYS + 0x03400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IDP_COREVOLT_PHYS (PXA_CS5_PHYS + 0x03800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IDP_CPLD_PHYS (PXA_CS5_PHYS + 0x03C00000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * virtual memory map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IDP_COREVOLT_VIRT (0xf0000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IDP_COREVOLT_SIZE (1*1024*1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IDP_CPLD_VIRT (IDP_COREVOLT_VIRT + IDP_COREVOLT_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IDP_CPLD_SIZE (1*1024*1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #if (IDP_CPLD_VIRT + IDP_CPLD_SIZE) > 0xfc000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #error Your custom IO space is getting a bit large !!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CPLD_P2V(x) ((x) - IDP_CPLD_PHYS + IDP_CPLD_VIRT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CPLD_V2P(x) ((x) - IDP_CPLD_VIRT + IDP_CPLD_PHYS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) # define __CPLD_REG(x) (*((volatile unsigned long *)CPLD_P2V(x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) # define __CPLD_REG(x) CPLD_P2V(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* board level registers in the CPLD: (offsets from CPLD_VIRT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define _IDP_CPLD_REV (IDP_CPLD_PHYS + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define _IDP_CPLD_PERIPH_PWR (IDP_CPLD_PHYS + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define _IDP_CPLD_LED_CONTROL (IDP_CPLD_PHYS + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define _IDP_CPLD_KB_COL_HIGH (IDP_CPLD_PHYS + 0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define _IDP_CPLD_KB_COL_LOW (IDP_CPLD_PHYS + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define _IDP_CPLD_PCCARD_EN (IDP_CPLD_PHYS + 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define _IDP_CPLD_GPIOH_DIR (IDP_CPLD_PHYS + 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define _IDP_CPLD_GPIOH_VALUE (IDP_CPLD_PHYS + 0x1C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define _IDP_CPLD_GPIOL_DIR (IDP_CPLD_PHYS + 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define _IDP_CPLD_GPIOL_VALUE (IDP_CPLD_PHYS + 0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define _IDP_CPLD_PCCARD_PWR (IDP_CPLD_PHYS + 0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define _IDP_CPLD_MISC_CTRL (IDP_CPLD_PHYS + 0x2C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define _IDP_CPLD_LCD (IDP_CPLD_PHYS + 0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define _IDP_CPLD_FLASH_WE (IDP_CPLD_PHYS + 0x34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define _IDP_CPLD_KB_ROW (IDP_CPLD_PHYS + 0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define _IDP_CPLD_PCCARD0_STATUS (IDP_CPLD_PHYS + 0x54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define _IDP_CPLD_PCCARD1_STATUS (IDP_CPLD_PHYS + 0x58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define _IDP_CPLD_MISC_STATUS (IDP_CPLD_PHYS + 0x5C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* FPGA register virtual addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define IDP_CPLD_REV __CPLD_REG(_IDP_CPLD_REV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define IDP_CPLD_PERIPH_PWR __CPLD_REG(_IDP_CPLD_PERIPH_PWR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define IDP_CPLD_LED_CONTROL __CPLD_REG(_IDP_CPLD_LED_CONTROL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define IDP_CPLD_KB_COL_HIGH __CPLD_REG(_IDP_CPLD_KB_COL_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define IDP_CPLD_KB_COL_LOW __CPLD_REG(_IDP_CPLD_KB_COL_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define IDP_CPLD_PCCARD_EN __CPLD_REG(_IDP_CPLD_PCCARD_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define IDP_CPLD_GPIOH_DIR __CPLD_REG(_IDP_CPLD_GPIOH_DIR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IDP_CPLD_GPIOH_VALUE __CPLD_REG(_IDP_CPLD_GPIOH_VALUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define IDP_CPLD_GPIOL_DIR __CPLD_REG(_IDP_CPLD_GPIOL_DIR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IDP_CPLD_GPIOL_VALUE __CPLD_REG(_IDP_CPLD_GPIOL_VALUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define IDP_CPLD_PCCARD_PWR __CPLD_REG(_IDP_CPLD_PCCARD_PWR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define IDP_CPLD_MISC_CTRL __CPLD_REG(_IDP_CPLD_MISC_CTRL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define IDP_CPLD_LCD __CPLD_REG(_IDP_CPLD_LCD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define IDP_CPLD_FLASH_WE __CPLD_REG(_IDP_CPLD_FLASH_WE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define IDP_CPLD_KB_ROW __CPLD_REG(_IDP_CPLD_KB_ROW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define IDP_CPLD_PCCARD0_STATUS __CPLD_REG(_IDP_CPLD_PCCARD0_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IDP_CPLD_PCCARD1_STATUS __CPLD_REG(_IDP_CPLD_PCCARD1_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define IDP_CPLD_MISC_STATUS __CPLD_REG(_IDP_CPLD_MISC_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * Bit masks for various registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) // IDP_CPLD_PCCARD_PWR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PCC0_PWR0 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PCC0_PWR1 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PCC0_PWR2 (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PCC0_PWR3 (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PCC1_PWR0 (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PCC1_PWR1 (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PCC1_PWR2 (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PCC1_PWR3 (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) // IDP_CPLD_PCCARD_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PCC0_RESET (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PCC1_RESET (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PCC0_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PCC1_ENABLE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) // IDP_CPLD_PCCARDx_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define _PCC_WRPROT (1 << 7) // 7-4 read as low true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define _PCC_RESET (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define _PCC_IRQ (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define _PCC_INPACK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PCC_BVD2 (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PCC_BVD1 (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PCC_VS2 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PCC_VS1 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* A listing of interrupts used by external hardware devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define TOUCH_PANEL_IRQ PXA_GPIO_TO_IRQ(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define IDE_IRQ PXA_GPIO_TO_IRQ(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define TOUCH_PANEL_IRQ_EDGE IRQ_TYPE_EDGE_FALLING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define ETHERNET_IRQ PXA_GPIO_TO_IRQ(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define ETHERNET_IRQ_EDGE IRQ_TYPE_EDGE_RISING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define PCMCIA_S0_CD_VALID PXA_GPIO_TO_IRQ(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PCMCIA_S0_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define PCMCIA_S1_CD_VALID PXA_GPIO_TO_IRQ(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PCMCIA_S1_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PCMCIA_S0_RDYINT PXA_GPIO_TO_IRQ(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define PCMCIA_S1_RDYINT PXA_GPIO_TO_IRQ(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * Macros for LED Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* leds 0 = ON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define IDP_HB_LED (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define IDP_BUSY_LED (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define IDP_LEDS_MASK (IDP_HB_LED | IDP_BUSY_LED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * macros for MTD driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define FLASH_WRITE_PROTECT_DISABLE() ((IDP_CPLD_FLASH_WE) &= ~(0x1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define FLASH_WRITE_PROTECT_ENABLE() ((IDP_CPLD_FLASH_WE) |= (0x1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * macros for matrix keyboard driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define KEYBD_MATRIX_NUMBER_INPUTS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define KEYBD_MATRIX_NUMBER_OUTPUTS 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define KEYBD_MATRIX_INVERT_OUTPUT_LOGIC FALSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define KEYBD_MATRIX_INVERT_INPUT_LOGIC FALSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define KEYBD_MATRIX_SETTLING_TIME_US 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define KEYBD_MATRIX_KEYSTATE_DEBOUNCE_CONSTANT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define KEYBD_MATRIX_SET_OUTPUTS(outputs) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) IDP_CPLD_KB_COL_LOW = outputs;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) IDP_CPLD_KB_COL_HIGH = outputs >> 7;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define KEYBD_MATRIX_GET_INPUTS(inputs) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) inputs = (IDP_CPLD_KB_ROW & 0x7f);\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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