^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mach-pxa/icontrol.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Support for the iControl and SafeTcam platforms from TMT Services
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * using the Embedian MXM-8x10 Computer on Module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2009 TMT Services & Supplies (Pty) Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * 2010-01-21 Hennie van der Merve <hvdmerwe@tmtservies.co.za>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "pxa320.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "mxm8x10.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/spi/pxa2xx_spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "generic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ICONTROL_MCP251x_nCS1 (15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ICONTROL_MCP251x_nCS2 (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ICONTROL_MCP251x_nCS3 (17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ICONTROL_MCP251x_nCS4 (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ICONTROL_MCP251x_nIRQ1 (74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ICONTROL_MCP251x_nIRQ2 (75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ICONTROL_MCP251x_nIRQ3 (76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ICONTROL_MCP251x_nIRQ4 (77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static struct pxa2xx_spi_chip mcp251x_chip_info1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .tx_threshold = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .rx_threshold = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .dma_burst_size = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .timeout = 235,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .gpio_cs = ICONTROL_MCP251x_nCS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static struct pxa2xx_spi_chip mcp251x_chip_info2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .tx_threshold = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .rx_threshold = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .dma_burst_size = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .timeout = 235,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .gpio_cs = ICONTROL_MCP251x_nCS2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static struct pxa2xx_spi_chip mcp251x_chip_info3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .tx_threshold = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .rx_threshold = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .dma_burst_size = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .timeout = 235,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .gpio_cs = ICONTROL_MCP251x_nCS3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static struct pxa2xx_spi_chip mcp251x_chip_info4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .tx_threshold = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .rx_threshold = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .dma_burst_size = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .timeout = 235,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .gpio_cs = ICONTROL_MCP251x_nCS4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static const struct property_entry mcp251x_properties[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) PROPERTY_ENTRY_U32("clock-frequency", 16000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static struct spi_board_info mcp251x_board_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .modalias = "mcp2515",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .max_speed_hz = 6500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .bus_num = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .chip_select = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .properties = mcp251x_properties,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .controller_data = &mcp251x_chip_info1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .irq = PXA_GPIO_TO_IRQ(ICONTROL_MCP251x_nIRQ1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .modalias = "mcp2515",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .max_speed_hz = 6500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .bus_num = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .chip_select = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .properties = mcp251x_properties,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .controller_data = &mcp251x_chip_info2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .irq = PXA_GPIO_TO_IRQ(ICONTROL_MCP251x_nIRQ2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .modalias = "mcp2515",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .max_speed_hz = 6500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .bus_num = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .chip_select = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .properties = mcp251x_properties,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .controller_data = &mcp251x_chip_info3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .irq = PXA_GPIO_TO_IRQ(ICONTROL_MCP251x_nIRQ3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .modalias = "mcp2515",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .max_speed_hz = 6500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .bus_num = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .chip_select = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .properties = mcp251x_properties,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .controller_data = &mcp251x_chip_info4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .irq = PXA_GPIO_TO_IRQ(ICONTROL_MCP251x_nIRQ4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static struct pxa2xx_spi_controller pxa_ssp3_spi_master_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .num_chipselect = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .enable_dma = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static struct pxa2xx_spi_controller pxa_ssp4_spi_master_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .num_chipselect = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .enable_dma = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct platform_device pxa_spi_ssp3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .name = "pxa2xx-spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .id = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .platform_data = &pxa_ssp3_spi_master_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct platform_device pxa_spi_ssp4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .name = "pxa2xx-spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .id = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .platform_data = &pxa_ssp4_spi_master_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static struct platform_device *icontrol_spi_devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) &pxa_spi_ssp3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) &pxa_spi_ssp4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static mfp_cfg_t mfp_can_cfg[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* CAN CS lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) GPIO15_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) GPIO16_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) GPIO17_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) GPIO24_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* SPI (SSP3) lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) GPIO89_SSP3_SCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) GPIO91_SSP3_TXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) GPIO92_SSP3_RXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* SPI (SSP4) lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) GPIO93_SSP4_SCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) GPIO95_SSP4_TXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) GPIO96_SSP4_RXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* CAN nIRQ lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) GPIO74_GPIO | MFP_LPM_EDGE_RISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) GPIO75_GPIO | MFP_LPM_EDGE_RISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) GPIO76_GPIO | MFP_LPM_EDGE_RISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) GPIO77_GPIO | MFP_LPM_EDGE_RISE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static void __init icontrol_can_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) pxa3xx_mfp_config(ARRAY_AND_SIZE(mfp_can_cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) platform_add_devices(ARRAY_AND_SIZE(icontrol_spi_devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) spi_register_board_info(ARRAY_AND_SIZE(mcp251x_board_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static void __init icontrol_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) mxm_8x10_barebones_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) mxm_8x10_usb_host_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) mxm_8x10_mmc_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) icontrol_can_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) regulator_has_full_constraints();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) MACHINE_START(ICONTROL, "iControl/SafeTcam boards using Embedian MXM-8x10 CoM")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .atag_offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .map_io = pxa3xx_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .nr_irqs = PXA_NR_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .init_irq = pxa3xx_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .handle_irq = pxa3xx_handle_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .init_time = pxa_timer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .init_machine = icontrol_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .restart = pxa_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) MACHINE_END
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags