^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Hardware definitions for HP iPAQ h5xxx Handheld Computers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2000-2003 Hewlett-Packard Company.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2002 Jamey Hicks <jamey.hicks@hp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2004-2005 Phil Blundell <pb@handhelds.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright 2007-2008 Anton Vorontsov <cbouatmailru@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * FITNESS FOR ANY PARTICULAR PURPOSE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Author: Jamey Hicks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mtd/partitions.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mtd/physmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "pxa25x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "h5000.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "udc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <mach/smemc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "generic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Flash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static struct mtd_partition h5000_flash0_partitions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .name = "bootldr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .size = 0x00040000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .mask_flags = MTD_WRITEABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .name = "root",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .size = MTDPART_SIZ_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static struct mtd_partition h5000_flash1_partitions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .name = "second root",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .size = SZ_16M - 0x00040000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .name = "asset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .size = MTDPART_SIZ_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .mask_flags = MTD_WRITEABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static struct physmap_flash_data h5000_flash0_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .parts = h5000_flash0_partitions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .nr_parts = ARRAY_SIZE(h5000_flash0_partitions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static struct physmap_flash_data h5000_flash1_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .parts = h5000_flash1_partitions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .nr_parts = ARRAY_SIZE(h5000_flash1_partitions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static struct resource h5000_flash0_resources = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .start = PXA_CS0_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .end = PXA_CS0_PHYS + SZ_32M - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static struct resource h5000_flash1_resources = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .start = PXA_CS0_PHYS + SZ_32M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .end = PXA_CS0_PHYS + SZ_32M + SZ_16M - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static struct platform_device h5000_flash[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .name = "physmap-flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .resource = &h5000_flash0_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .num_resources = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .platform_data = &h5000_flash0_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .name = "physmap-flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .resource = &h5000_flash1_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .num_resources = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .platform_data = &h5000_flash1_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * USB Device Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static struct pxa2xx_udc_mach_info h5000_udc_mach_info __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .gpio_pullup = H5000_GPIO_USB_PULLUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * GPIO setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static unsigned long h5000_pin_config[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Crystal and Clock Signals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) GPIO12_32KHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* SDRAM and Static Memory I/O Signals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) GPIO15_nCS_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) GPIO78_nCS_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) GPIO79_nCS_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) GPIO80_nCS_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* FFUART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) GPIO34_FFUART_RXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) GPIO35_FFUART_CTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) GPIO36_FFUART_DCD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) GPIO37_FFUART_DSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) GPIO38_FFUART_RI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) GPIO39_FFUART_TXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) GPIO40_FFUART_DTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) GPIO41_FFUART_RTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* BTUART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) GPIO42_BTUART_RXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) GPIO43_BTUART_TXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) GPIO44_BTUART_CTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) GPIO45_BTUART_RTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* SSP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) GPIO23_SSP1_SCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) GPIO25_SSP1_TXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) GPIO26_SSP1_RXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* I2S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) GPIO28_I2S_BITCLK_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) GPIO29_I2S_SDATA_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) GPIO30_I2S_SDATA_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) GPIO31_I2S_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) GPIO32_I2S_SYSCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * Localbus setup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * CS0: Flash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * CS1: MediaQ chip, select 16-bit bus and vlio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * CS5: SAMCOP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static void fix_msc(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) __raw_writel(0x129c24f2, MSC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) __raw_writel(0x7ff424fa, MSC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) __raw_writel(0x7ff47ff4, MSC2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) __raw_writel(__raw_readl(MDREFR) | 0x02080000, MDREFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * Platform devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static struct platform_device *devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) &h5000_flash[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) &h5000_flash[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static void __init h5000_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) fix_msc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) pxa2xx_mfp_config(ARRAY_AND_SIZE(h5000_pin_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) pxa_set_ffuart_info(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) pxa_set_btuart_info(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) pxa_set_stuart_info(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) pxa_set_udc_info(&h5000_udc_mach_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) platform_add_devices(ARRAY_AND_SIZE(devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) MACHINE_START(H5400, "HP iPAQ H5000")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .atag_offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .map_io = pxa25x_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .nr_irqs = PXA_NR_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .init_irq = pxa25x_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .handle_irq = pxa25x_handle_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .init_time = pxa_timer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .init_machine = h5000_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .restart = pxa_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) MACHINE_END
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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