^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * arch/arm/mach-pxa/include/mach/gumstix.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <mach/irqs.h> /* PXA_GPIO_TO_IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /* BTRESET - Reset line to Bluetooth module, active low signal. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define GPIO_GUMSTIX_BTRESET 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define GPIO_GUMSTIX_BTRESET_MD (GPIO_GUMSTIX_BTRESET | GPIO_OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) GPIOn - Input from MAX823 (or equiv), normalizing USB +5V into a clean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) interrupt signal for determining cable presence. On the gumstix F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) this moves to GPIO17 and GPIO37. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* GPIOx - Connects to USB D+ and used as a pull-up after GPIOn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) has detected a cable insertion; driven low otherwise. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define GPIO_GUMSTIX_USB_GPIOn 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define GPIO_GUMSTIX_USB_GPIOx 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* usb state change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define GUMSTIX_USB_INTR_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_USB_GPIOn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define GPIO_GUMSTIX_USB_GPIOn_MD (GPIO_GUMSTIX_USB_GPIOn | GPIO_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define GPIO_GUMSTIX_USB_GPIOx_CON_MD (GPIO_GUMSTIX_USB_GPIOx | GPIO_OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define GPIO_GUMSTIX_USB_GPIOx_DIS_MD (GPIO_GUMSTIX_USB_GPIOx | GPIO_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * SD/MMC definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define GUMSTIX_GPIO_nSD_WP 22 /* SD Write Protect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define GUMSTIX_GPIO_nSD_DETECT 11 /* MMC/SD Card Detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define GUMSTIX_IRQ_GPIO_nSD_DETECT PXA_GPIO_TO_IRQ(GUMSTIX_GPIO_nSD_DETECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * SMC Ethernet definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * ETH_RST provides a hardware reset line to the ethernet chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * ETH is the IRQ line in from the ethernet chip to the PXA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GPIO_GUMSTIX_ETH0_RST 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define GPIO_GUMSTIX_ETH0_RST_MD (GPIO_GUMSTIX_ETH0_RST | GPIO_OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GPIO_GUMSTIX_ETH1_RST 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define GPIO_GUMSTIX_ETH1_RST_MD (GPIO_GUMSTIX_ETH1_RST | GPIO_OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GPIO_GUMSTIX_ETH0 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GPIO_GUMSTIX_ETH0_MD (GPIO_GUMSTIX_ETH0 | GPIO_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GUMSTIX_ETH0_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_ETH0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GPIO_GUMSTIX_ETH1 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GPIO_GUMSTIX_ETH1_MD (GPIO_GUMSTIX_ETH1 | GPIO_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GUMSTIX_ETH1_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_ETH1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* CF reset line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GPIO8_RESET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* CF slot 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define GPIO4_nBVD1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GPIO4_nSTSCHG GPIO4_nBVD1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define GPIO11_nCD 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define GPIO26_PRDY_nBSY 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GUMSTIX_S0_nSTSCHG_IRQ PXA_GPIO_TO_IRQ(GPIO4_nSTSCHG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define GUMSTIX_S0_nCD_IRQ PXA_GPIO_TO_IRQ(GPIO11_nCD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GUMSTIX_S0_PRDY_nBSY_IRQ PXA_GPIO_TO_IRQ(GPIO26_PRDY_nBSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* CF slot 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define GPIO18_nBVD1 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define GPIO18_nSTSCHG GPIO18_nBVD1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define GPIO36_nCD 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define GPIO27_PRDY_nBSY 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define GUMSTIX_S1_nSTSCHG_IRQ PXA_GPIO_TO_IRQ(GPIO18_nSTSCHG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define GUMSTIX_S1_nCD_IRQ PXA_GPIO_TO_IRQ(GPIO36_nCD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define GUMSTIX_S1_PRDY_nBSY_IRQ PXA_GPIO_TO_IRQ(GPIO27_PRDY_nBSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* CF GPIO line modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define GPIO4_nSTSCHG_MD (GPIO4_nSTSCHG | GPIO_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define GPIO8_RESET_MD (GPIO8_RESET | GPIO_OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GPIO11_nCD_MD (GPIO11_nCD | GPIO_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define GPIO18_nSTSCHG_MD (GPIO18_nSTSCHG | GPIO_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define GPIO26_PRDY_nBSY_MD (GPIO26_PRDY_nBSY | GPIO_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define GPIO27_PRDY_nBSY_MD (GPIO27_PRDY_nBSY | GPIO_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define GPIO36_nCD_MD (GPIO36_nCD | GPIO_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* for expansion boards that can't be programatically detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) extern int am200_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) extern int am300_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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