Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *  linux/arch/arm/mach-pxa/generic.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Author:	Nicolas Pitre
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright:	MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) struct irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) extern unsigned int get_clk_frequency_khz(int info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 					     unsigned int));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) extern void __init pxa_map_io(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) extern void pxa_timer_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SET_BANK(__nr,__start,__size) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	mi->bank[__nr].start = (__start), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	mi->bank[__nr].size = (__size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ARRAY_AND_SIZE(x)	(x), ARRAY_SIZE(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define pxa25x_handle_irq icip_handle_irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) extern int __init pxa25x_clocks_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) extern void __init pxa25x_init_irq(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) extern void __init pxa25x_map_io(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) extern void __init pxa26x_init_irq(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define pxa27x_handle_irq ichp_handle_irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) extern int __init pxa27x_clocks_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) extern unsigned	pxa27x_get_clk_frequency_khz(int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) extern void __init pxa27x_init_irq(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) extern void __init pxa27x_map_io(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define pxa3xx_handle_irq ichp_handle_irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) extern int __init pxa3xx_clocks_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) extern void __init pxa3xx_init_irq(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) extern void __init pxa3xx_map_io(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) extern struct syscore_ops pxa_irq_syscore_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) extern struct syscore_ops pxa2xx_mfp_syscore_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) extern struct syscore_ops pxa3xx_mfp_syscore_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) void __init pxa_set_ffuart_info(void *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) void __init pxa_set_btuart_info(void *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) void __init pxa_set_stuart_info(void *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) void __init pxa_set_hwuart_info(void *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) void pxa_restart(enum reboot_mode, const char *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) extern void pxa2xx_clear_reset_status(unsigned int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static inline void pxa2xx_clear_reset_status(unsigned int mask) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)  * Once fully converted to the clock framework, all these functions should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)  * removed, and replaced with a clk_get(NULL, "core").
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #ifdef CONFIG_PXA25x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) extern unsigned pxa25x_get_clk_frequency_khz(int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define pxa25x_get_clk_frequency_khz(x)		(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #ifdef CONFIG_PXA27x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define pxa27x_get_clk_frequency_khz(x)		(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #ifdef CONFIG_PXA3xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) extern unsigned	pxa3xx_get_clk_frequency_khz(int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define pxa3xx_get_clk_frequency_khz(x)		(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #endif