Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *  linux/arch/arm/mach-pxa/generic.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *  Author:	Nicolas Pitre
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *  Created:	Jun 15, 2001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *  Copyright:	MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * Code common to all PXA machines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * Since this file should be linked before any other machine specific file,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  * the __initcall() here will be executed first.  This serves as default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  * initialization stuff for PXA machines which can be overridden later if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * need be.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <mach/irqs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <mach/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <mach/smemc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <mach/pxa3xx-regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "generic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <clocksource/pxa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) void clear_reset_status(unsigned int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	if (cpu_is_pxa2xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		pxa2xx_clear_reset_status(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		/* RESET_STATUS_* has a 1:1 mapping with ARSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		ARSR = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)  * For non device-tree builds, keep legacy timer init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) void __init pxa_timer_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	if (cpu_is_pxa25x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		pxa25x_clocks_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	if (cpu_is_pxa27x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		pxa27x_clocks_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	if (cpu_is_pxa3xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		pxa3xx_clocks_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x40a00000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)  * Get the clock frequency as reflected by CCCR and the turbo flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)  * We assume these values have been applied via a fcs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)  * If info is not 0 we also display the current settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int get_clk_frequency_khz(int info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	if (cpu_is_pxa25x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 		return pxa25x_get_clk_frequency_khz(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	else if (cpu_is_pxa27x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 		return pxa27x_get_clk_frequency_khz(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) EXPORT_SYMBOL(get_clk_frequency_khz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)  * Intel PXA2xx internal register mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)  * Note: virtual 0xfffe0000-0xffffffff is reserved for the vector table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)  *       and cache flush area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static struct map_desc common_io_desc[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)   	{	/* Devs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 		.virtual	= (unsigned long)PERIPH_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 		.pfn		= __phys_to_pfn(PERIPH_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 		.length		= PERIPH_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 		.type		= MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) void __init pxa_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 	debug_ll_io_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 	iotable_init(ARRAY_AND_SIZE(common_io_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }