Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * sleep mode for CSR SiRFprimaII
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "pm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define DENALI_CTL_22_OFF	0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DENALI_CTL_112_OFF	0x1c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	.text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) ENTRY(sirfsoc_finish_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	@ r5: 	mem controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	ldr     r0, =sirfsoc_memc_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	ldr	r5, [r0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	@ r6: 	pwrc base offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	ldr     r0, =sirfsoc_pwrc_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	ldr	r6, [r0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	@ r7: 	rtc iobrg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	ldr     r0, =sirfsoc_rtciobrg_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	ldr	r7, [r0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	@ Read the power control register and set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	@ sleep force bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	add	r0, r6, #SIRFSOC_PWRC_PDN_CTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	bl	__sirfsoc_rtc_iobrg_readl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	orr	r0,r0,#SIRFSOC_PWR_SLEEPFORCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	add	r1, r6, #SIRFSOC_PWRC_PDN_CTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	bl	sirfsoc_rtc_iobrg_pre_writel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	mov	r1, #0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	@ read the MEM ctl register and set the self
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	@ refresh bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	ldr	r2, [r5, #DENALI_CTL_22_OFF]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	orr	r2, r2, #0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	@ Following code has to run from cache since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	@ the RAM is going to self refresh mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	.align 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	str	r2, [r5, #DENALI_CTL_22_OFF]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	ldr	r4, [r5, #DENALI_CTL_112_OFF]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	tst	r4, #0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	bne	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	@ write SLEEPFORCE through rtc iobridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	str	r1, [r7]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	@ wait rtc io bridge sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	ldr	r3, [r7]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	tst	r3, #0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	bne	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	b .