^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * reset controller for CSR SiRFprimaII
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/system_misc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SIRFSOC_RSTBIT_NUM 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static void __iomem *sirfsoc_rstc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static DEFINE_MUTEX(rstc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static int sirfsoc_reset_module(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) unsigned long sw_reset_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u32 reset_bit = sw_reset_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) if (reset_bit >= SIRFSOC_RSTBIT_NUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) mutex_lock(&rstc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Writing 1 to this bit resets corresponding block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Writing 0 to this bit de-asserts reset signal of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * corresponding block. datasheet doesn't require explicit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * delay between the set and clear of reset bit. it could
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * be shorter if tests pass.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) writel(readl(sirfsoc_rstc_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) (reset_bit / 32) * 4) | (1 << reset_bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) sirfsoc_rstc_base + (reset_bit / 32) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) writel(readl(sirfsoc_rstc_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) (reset_bit / 32) * 4) & ~(1 << reset_bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) sirfsoc_rstc_base + (reset_bit / 32) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) mutex_unlock(&rstc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static struct reset_control_ops sirfsoc_rstc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .reset = sirfsoc_reset_module,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static struct reset_controller_dev sirfsoc_reset_controller = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .ops = &sirfsoc_rstc_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .nr_resets = SIRFSOC_RSTBIT_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SIRFSOC_SYS_RST_BIT BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static int sirfsoc_restart(struct notifier_block *nb, unsigned long action,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) writel(SIRFSOC_SYS_RST_BIT, sirfsoc_rstc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static struct notifier_block sirfsoc_restart_nb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .notifier_call = sirfsoc_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .priority = 192,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static int sirfsoc_rstc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) sirfsoc_rstc_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (!sirfsoc_rstc_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) dev_err(&pdev->dev, "unable to map rstc cpu registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) sirfsoc_reset_controller.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) register_restart_handler(&sirfsoc_restart_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (IS_ENABLED(CONFIG_RESET_CONTROLLER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) reset_controller_register(&sirfsoc_reset_controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static const struct of_device_id rstc_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { .compatible = "sirf,prima2-rstc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static struct platform_driver sirfsoc_rstc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .probe = sirfsoc_rstc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .name = "sirfsoc_rstc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .of_match_table = rstc_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int __init sirfsoc_rstc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return platform_driver_register(&sirfsoc_rstc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) subsys_initcall(sirfsoc_rstc_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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