^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * arch/arm/mach-prima2/pm.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _MACH_PRIMA2_PM_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _MACH_PRIMA2_PM_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define SIRFSOC_PWR_SLEEPFORCE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define SIRFSOC_SLEEP_MODE_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SIRFSOC_DEEP_SLEEP_MODE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SIRFSOC_PWRC_PDN_CTRL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SIRFSOC_PWRC_PON_OFF 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SIRFSOC_PWRC_TRIGGER_EN 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SIRFSOC_PWRC_PIN_STATUS 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SIRFSOC_PWRC_SCRATCH_PAD1 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SIRFSOC_PWRC_SCRATCH_PAD2 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) extern int sirfsoc_finish_suspend(unsigned long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)