^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * power management entry for CSR SiRFprimaII
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/rtc/sirfsoc_rtciobrg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/outercache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/hardware/cache-l2x0.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "pm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * suspend asm codes will access these to make DRAM become self-refresh and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * system sleep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u32 sirfsoc_pwrc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) void __iomem *sirfsoc_memc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static void sirfsoc_set_wakeup_source(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 pwr_trigger_en_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) pwr_trigger_en_reg = sirfsoc_rtc_iobrg_readl(sirfsoc_pwrc_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) SIRFSOC_PWRC_TRIGGER_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define X_ON_KEY_B (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RTC_ALARM0_B (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RTC_ALARM1_B (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) sirfsoc_rtc_iobrg_writel(pwr_trigger_en_reg | X_ON_KEY_B |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) RTC_ALARM0_B | RTC_ALARM1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) sirfsoc_pwrc_base + SIRFSOC_PWRC_TRIGGER_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static void sirfsoc_set_sleep_mode(u32 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u32 sleep_mode = sirfsoc_rtc_iobrg_readl(sirfsoc_pwrc_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) SIRFSOC_PWRC_PDN_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) sleep_mode &= ~(SIRFSOC_SLEEP_MODE_MASK << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) sleep_mode |= mode << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) sirfsoc_rtc_iobrg_writel(sleep_mode, sirfsoc_pwrc_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) SIRFSOC_PWRC_PDN_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static int sirfsoc_pre_suspend_power_off(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 wakeup_entry = __pa_symbol(cpu_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) sirfsoc_rtc_iobrg_writel(wakeup_entry, sirfsoc_pwrc_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) SIRFSOC_PWRC_SCRATCH_PAD1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) sirfsoc_set_wakeup_source();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) sirfsoc_set_sleep_mode(SIRFSOC_DEEP_SLEEP_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static int sirfsoc_pm_enter(suspend_state_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) case PM_SUSPEND_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) sirfsoc_pre_suspend_power_off();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) outer_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* go zzz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) cpu_suspend(0, sirfsoc_finish_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) outer_resume();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static const struct platform_suspend_ops sirfsoc_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .enter = sirfsoc_pm_enter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .valid = suspend_valid_only_mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static const struct of_device_id pwrc_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { .compatible = "sirf,prima2-pwrc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static int __init sirfsoc_of_pwrc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) np = of_find_matching_node(NULL, pwrc_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) pr_err("unable to find compatible sirf pwrc node in dtb\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * pwrc behind rtciobrg is not located in memory space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * though the property is named reg. reg only means base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * offset for pwrc. then of_iomap is not suitable here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (of_property_read_u32(np, "reg", &sirfsoc_pwrc_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) panic("unable to find base address of pwrc node in dtb\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static const struct of_device_id memc_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { .compatible = "sirf,prima2-memc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int sirfsoc_memc_probe(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct device_node *np = op->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) sirfsoc_memc_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (!sirfsoc_memc_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) panic("unable to map memc registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static struct platform_driver sirfsoc_memc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .probe = sirfsoc_memc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .name = "sirfsoc-memc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .of_match_table = memc_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int __init sirfsoc_memc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return platform_driver_register(&sirfsoc_memc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int __init sirfsoc_pm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) sirfsoc_of_pwrc_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) sirfsoc_memc_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) suspend_set_ops(&sirfsoc_pm_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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