^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * arch/arm/mach-orion5x/wnr854t-setup.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mtd/physmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mv643xx_eth.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_data/dsa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/mach/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "orion5x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "mpp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static unsigned int wnr854t_mpp_modes[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) MPP0_GPIO, /* Power LED green (0=on) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MPP1_GPIO, /* Reset Button (0=off) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MPP2_GPIO, /* Power LED blink (0=off) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MPP3_GPIO, /* WAN Status LED amber (0=off) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MPP4_GPIO, /* PCI int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MPP5_GPIO, /* ??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MPP6_GPIO, /* ??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MPP7_GPIO, /* ??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MPP8_UNUSED, /* ??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MPP9_GIGE, /* GE_RXERR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) MPP10_UNUSED, /* ??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MPP11_UNUSED, /* ??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MPP12_GIGE, /* GE_TXD[4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) MPP13_GIGE, /* GE_TXD[5] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) MPP14_GIGE, /* GE_TXD[6] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MPP15_GIGE, /* GE_TXD[7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MPP16_GIGE, /* GE_RXD[4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MPP17_GIGE, /* GE_RXD[5] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MPP18_GIGE, /* GE_RXD[6] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MPP19_GIGE, /* GE_RXD[7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * 8M NOR flash Device bus boot chip select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define WNR854T_NOR_BOOT_BASE 0xf4000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define WNR854T_NOR_BOOT_SIZE SZ_8M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static struct mtd_partition wnr854t_nor_flash_partitions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .name = "kernel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .offset = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .size = 0x00100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .name = "rootfs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .offset = 0x00100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .size = 0x00660000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .name = "uboot",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .offset = 0x00760000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .size = 0x00040000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static struct physmap_flash_data wnr854t_nor_flash_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .parts = wnr854t_nor_flash_partitions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .nr_parts = ARRAY_SIZE(wnr854t_nor_flash_partitions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static struct resource wnr854t_nor_flash_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .start = WNR854T_NOR_BOOT_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .end = WNR854T_NOR_BOOT_BASE + WNR854T_NOR_BOOT_SIZE - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static struct platform_device wnr854t_nor_flash = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .name = "physmap-flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .platform_data = &wnr854t_nor_flash_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .num_resources = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .resource = &wnr854t_nor_flash_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static struct mv643xx_eth_platform_data wnr854t_eth_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .phy_addr = MV643XX_ETH_PHY_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .speed = SPEED_1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .duplex = DUPLEX_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static struct dsa_chip_data wnr854t_switch_chip_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .port_names[0] = "lan3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .port_names[1] = "lan4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .port_names[2] = "wan",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .port_names[3] = "cpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .port_names[5] = "lan1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .port_names[7] = "lan2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void __init wnr854t_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * Setup basic Orion functions. Need to be called early.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) orion5x_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) orion5x_mpp_conf(wnr854t_mpp_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * Configure peripherals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) orion5x_eth_init(&wnr854t_eth_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) orion5x_eth_switch_init(&wnr854t_switch_chip_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) orion5x_uart0_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ORION_MBUS_DEVBUS_BOOT_ATTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) WNR854T_NOR_BOOT_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) WNR854T_NOR_BOOT_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) platform_device_register(&wnr854t_nor_flash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * Check for devices with hard-wired IRQs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) irq = orion5x_pci_map_irq(dev, slot, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (irq != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * Mini-PCI slot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (slot == 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return gpio_to_irq(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static struct hw_pci wnr854t_pci __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .nr_controllers = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .setup = orion5x_pci_sys_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .scan = orion5x_pci_sys_scan_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .map_irq = wnr854t_pci_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int __init wnr854t_pci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (machine_is_wnr854t())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) pci_common_init(&wnr854t_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) subsys_initcall(wnr854t_pci_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) MACHINE_START(WNR854T, "Netgear WNR854T")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .atag_offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .nr_irqs = ORION5X_NR_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .init_machine = wnr854t_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .map_io = orion5x_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .init_early = orion5x_init_early,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .init_irq = orion5x_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .init_time = orion5x_timer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .fixup = tag_fixup_mem32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .restart = orion5x_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) MACHINE_END
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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