^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * arch/arm/mach-orion5x/ts78xx-setup.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Maintainer: Alexander Clouter <alex@digriz.org.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mv643xx_eth.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/ata_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mtd/platnand.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/timeriomem-rng.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "mpp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "orion5x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "ts78xx-fpga.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * TS-78xx Info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * FPGA - lives where the PCI bus would be at ORION5X_PCI_MEM_PHYS_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TS78XX_FPGA_REGS_PHYS_BASE 0xe8000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TS78XX_FPGA_REGS_VIRT_BASE IOMEM(0xff900000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TS78XX_FPGA_REGS_SIZE SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static struct ts78xx_fpga_data ts78xx_fpga = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .state = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* .supports = ... - populated by ts78xx_fpga_supports() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * I/O Address Mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static struct map_desc ts78xx_io_desc[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .virtual = (unsigned long)TS78XX_FPGA_REGS_VIRT_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .pfn = __phys_to_pfn(TS78XX_FPGA_REGS_PHYS_BASE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .length = TS78XX_FPGA_REGS_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static void __init ts78xx_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) orion5x_map_io();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) iotable_init(ts78xx_io_desc, ARRAY_SIZE(ts78xx_io_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * Ethernet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static struct mv643xx_eth_platform_data ts78xx_eth_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .phy_addr = MV643XX_ETH_PHY_ADDR(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * SATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static struct mv_sata_platform_data ts78xx_sata_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .n_ports = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * RTC M48T86 - nicked^Wborrowed from arch/arm/mach-ep93xx/ts72xx.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TS_RTC_CTRL (TS78XX_FPGA_REGS_PHYS_BASE + 0x808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define TS_RTC_DATA (TS78XX_FPGA_REGS_PHYS_BASE + 0x80c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static struct resource ts78xx_ts_rtc_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) DEFINE_RES_MEM(TS_RTC_CTRL, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) DEFINE_RES_MEM(TS_RTC_DATA, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static struct platform_device ts78xx_ts_rtc_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .name = "rtc-m48t86",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .resource = ts78xx_ts_rtc_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .num_resources = ARRAY_SIZE(ts78xx_ts_rtc_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static int ts78xx_ts_rtc_load(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (ts78xx_fpga.supports.ts_rtc.init == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) rc = platform_device_register(&ts78xx_ts_rtc_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (!rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ts78xx_fpga.supports.ts_rtc.init = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) rc = platform_device_add(&ts78xx_ts_rtc_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) pr_info("RTC could not be registered: %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static void ts78xx_ts_rtc_unload(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) platform_device_del(&ts78xx_ts_rtc_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * NAND Flash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TS_NAND_CTRL (TS78XX_FPGA_REGS_VIRT_BASE + 0x800) /* VIRT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TS_NAND_DATA (TS78XX_FPGA_REGS_PHYS_BASE + 0x804) /* PHYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * hardware specific access to control-lines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * ctrl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * NAND_NCE: bit 0 -> bit 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * NAND_CLE: bit 1 -> bit 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * NAND_ALE: bit 2 -> bit 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static void ts78xx_ts_nand_cmd_ctrl(struct nand_chip *this, int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned int ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (ctrl & NAND_CTRL_CHANGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned char bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) bits = (ctrl & NAND_NCE) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) bits |= ctrl & NAND_CLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) bits |= (ctrl & NAND_ALE) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) writeb((readb(TS_NAND_CTRL) & ~0x7) | bits, TS_NAND_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (cmd != NAND_CMD_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) writeb(cmd, this->legacy.IO_ADDR_W);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int ts78xx_ts_nand_dev_ready(struct nand_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return readb(TS_NAND_CTRL) & 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static void ts78xx_ts_nand_write_buf(struct nand_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) const uint8_t *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) void __iomem *io_base = chip->legacy.IO_ADDR_W;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned long off = ((unsigned long)buf & 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (off) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) sz = min_t(int, 4 - off, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) writesb(io_base, buf, sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) buf += sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) len -= sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) sz = len >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (sz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u32 *buf32 = (u32 *)buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) writesl(io_base, buf32, sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) buf += sz << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) len -= sz << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) writesb(io_base, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static void ts78xx_ts_nand_read_buf(struct nand_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) uint8_t *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) void __iomem *io_base = chip->legacy.IO_ADDR_R;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned long off = ((unsigned long)buf & 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (off) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) sz = min_t(int, 4 - off, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) readsb(io_base, buf, sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) buf += sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) len -= sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) sz = len >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (sz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u32 *buf32 = (u32 *)buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) readsl(io_base, buf32, sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) buf += sz << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) len -= sz << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) readsb(io_base, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static struct mtd_partition ts78xx_ts_nand_parts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .name = "mbr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .size = SZ_128K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .mask_flags = MTD_WRITEABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .name = "kernel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .size = SZ_4M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .name = "initrd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .size = SZ_4M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .name = "rootfs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .size = MTDPART_SIZ_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static struct platform_nand_data ts78xx_ts_nand_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .nr_chips = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .partitions = ts78xx_ts_nand_parts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .nr_partitions = ARRAY_SIZE(ts78xx_ts_nand_parts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .chip_delay = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .bbt_options = NAND_BBT_USE_FLASH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .ctrl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * The HW ECC offloading functions, used to give about a 9%
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * performance increase for 'dd if=/dev/mtdblockX' and 5% for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * nanddump. This all however was changed by git commit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * e6cf5df1838c28bb060ac45b5585e48e71bbc740 so now there is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * no performance advantage to be had so we no longer bother
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .cmd_ctrl = ts78xx_ts_nand_cmd_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .dev_ready = ts78xx_ts_nand_dev_ready,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .write_buf = ts78xx_ts_nand_write_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .read_buf = ts78xx_ts_nand_read_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static struct resource ts78xx_ts_nand_resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) = DEFINE_RES_MEM(TS_NAND_DATA, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static struct platform_device ts78xx_ts_nand_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .name = "gen_nand",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .platform_data = &ts78xx_ts_nand_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .resource = &ts78xx_ts_nand_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .num_resources = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static int ts78xx_ts_nand_load(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (ts78xx_fpga.supports.ts_nand.init == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) rc = platform_device_register(&ts78xx_ts_nand_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (!rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ts78xx_fpga.supports.ts_nand.init = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) rc = platform_device_add(&ts78xx_ts_nand_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) pr_info("NAND could not be registered: %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static void ts78xx_ts_nand_unload(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) platform_device_del(&ts78xx_ts_nand_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * HW RNG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define TS_RNG_DATA (TS78XX_FPGA_REGS_PHYS_BASE | 0x044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static struct resource ts78xx_ts_rng_resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) = DEFINE_RES_MEM(TS_RNG_DATA, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static struct timeriomem_rng_data ts78xx_ts_rng_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .period = 1000000, /* one second */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static struct platform_device ts78xx_ts_rng_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .name = "timeriomem_rng",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .platform_data = &ts78xx_ts_rng_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .resource = &ts78xx_ts_rng_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .num_resources = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static int ts78xx_ts_rng_load(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (ts78xx_fpga.supports.ts_rng.init == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) rc = platform_device_register(&ts78xx_ts_rng_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (!rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ts78xx_fpga.supports.ts_rng.init = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) rc = platform_device_add(&ts78xx_ts_rng_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) pr_info("RNG could not be registered: %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static void ts78xx_ts_rng_unload(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) platform_device_del(&ts78xx_ts_rng_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * FPGA 'hotplug' support code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static void ts78xx_fpga_devices_zero_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ts78xx_fpga.supports.ts_rtc.init = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ts78xx_fpga.supports.ts_nand.init = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ts78xx_fpga.supports.ts_rng.init = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static void ts78xx_fpga_supports(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* TODO: put this 'table' into ts78xx-fpga.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) switch (ts78xx_fpga.id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) case TS7800_REV_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) case TS7800_REV_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) case TS7800_REV_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) case TS7800_REV_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) case TS7800_REV_5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) case TS7800_REV_6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) case TS7800_REV_7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) case TS7800_REV_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) case TS7800_REV_9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ts78xx_fpga.supports.ts_rtc.present = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ts78xx_fpga.supports.ts_nand.present = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ts78xx_fpga.supports.ts_rng.present = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* enable devices if magic matches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) switch ((ts78xx_fpga.id >> 8) & 0xffffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) case TS7800_FPGA_MAGIC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) pr_warn("unrecognised FPGA revision 0x%.2x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ts78xx_fpga.id & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ts78xx_fpga.supports.ts_rtc.present = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ts78xx_fpga.supports.ts_nand.present = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ts78xx_fpga.supports.ts_rng.present = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ts78xx_fpga.supports.ts_rtc.present = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ts78xx_fpga.supports.ts_nand.present = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ts78xx_fpga.supports.ts_rng.present = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static int ts78xx_fpga_load_devices(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) int tmp, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (ts78xx_fpga.supports.ts_rtc.present == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) tmp = ts78xx_ts_rtc_load();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ts78xx_fpga.supports.ts_rtc.present = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ret |= tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (ts78xx_fpga.supports.ts_nand.present == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) tmp = ts78xx_ts_nand_load();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ts78xx_fpga.supports.ts_nand.present = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ret |= tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (ts78xx_fpga.supports.ts_rng.present == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) tmp = ts78xx_ts_rng_load();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ts78xx_fpga.supports.ts_rng.present = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ret |= tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static int ts78xx_fpga_unload_devices(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (ts78xx_fpga.supports.ts_rtc.present == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ts78xx_ts_rtc_unload();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (ts78xx_fpga.supports.ts_nand.present == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) ts78xx_ts_nand_unload();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (ts78xx_fpga.supports.ts_rng.present == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ts78xx_ts_rng_unload();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static int ts78xx_fpga_load(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ts78xx_fpga.id = readl(TS78XX_FPGA_REGS_VIRT_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) pr_info("FPGA magic=0x%.6x, rev=0x%.2x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) (ts78xx_fpga.id >> 8) & 0xffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ts78xx_fpga.id & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ts78xx_fpga_supports();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (ts78xx_fpga_load_devices()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) ts78xx_fpga.state = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static int ts78xx_fpga_unload(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) unsigned int fpga_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) fpga_id = readl(TS78XX_FPGA_REGS_VIRT_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * There does not seem to be a feasible way to block access to the GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * pins from userspace (/dev/mem). This if clause should hopefully warn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * those foolish enough not to follow 'policy' :)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * UrJTAG SVN since r1381 can be used to reprogram the FPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (ts78xx_fpga.id != fpga_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) pr_err("FPGA magic/rev mismatch\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) "TS-78xx FPGA: was 0x%.6x/%.2x but now 0x%.6x/%.2x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) (ts78xx_fpga.id >> 8) & 0xffffff, ts78xx_fpga.id & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) (fpga_id >> 8) & 0xffffff, fpga_id & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ts78xx_fpga.state = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (ts78xx_fpga_unload_devices()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ts78xx_fpga.state = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static ssize_t ts78xx_fpga_show(struct kobject *kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct kobj_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (ts78xx_fpga.state < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return sprintf(buf, "borked\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return sprintf(buf, "%s\n", (ts78xx_fpga.state) ? "online" : "offline");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static ssize_t ts78xx_fpga_store(struct kobject *kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct kobj_attribute *attr, const char *buf, size_t n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) int value, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (ts78xx_fpga.state < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) pr_err("FPGA borked, you must powercycle ASAP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (strncmp(buf, "online", sizeof("online") - 1) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) value = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) else if (strncmp(buf, "offline", sizeof("offline") - 1) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (ts78xx_fpga.state == value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) ret = (ts78xx_fpga.state == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) ? ts78xx_fpga_load()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) : ts78xx_fpga_unload();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (!(ret < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ts78xx_fpga.state = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static struct kobj_attribute ts78xx_fpga_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) __ATTR(ts78xx_fpga, 0644, ts78xx_fpga_show, ts78xx_fpga_store);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * General Setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static unsigned int ts78xx_mpp_modes[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) MPP0_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) MPP1_GPIO, /* JTAG Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) MPP2_GPIO, /* JTAG Data In */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) MPP3_GPIO, /* Lat ECP2 256 FPGA - PB2B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) MPP4_GPIO, /* JTAG Data Out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) MPP5_GPIO, /* JTAG TMS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) MPP6_GPIO, /* Lat ECP2 256 FPGA - PB31A_CLK4+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) MPP7_GPIO, /* Lat ECP2 256 FPGA - PB22B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) MPP8_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) MPP9_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) MPP10_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) MPP11_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) MPP12_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) MPP13_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) MPP14_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) MPP15_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) MPP16_UART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) MPP17_UART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) MPP18_UART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) MPP19_UART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * MPP[20] PCI Clock Out 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * MPP[21] PCI Clock Out 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * MPP[22] Unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * MPP[23] Unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * MPP[24] Unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * MPP[25] Unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static void __init ts78xx_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * Setup basic Orion functions. Need to be called early.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) orion5x_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) orion5x_mpp_conf(ts78xx_mpp_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * Configure peripherals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) orion5x_ehci0_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) orion5x_ehci1_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) orion5x_eth_init(&ts78xx_eth_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) orion5x_sata_init(&ts78xx_sata_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) orion5x_uart0_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) orion5x_uart1_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) orion5x_xor_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* FPGA init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ts78xx_fpga_devices_zero_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) ret = ts78xx_fpga_load();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ret = sysfs_create_file(firmware_kobj, &ts78xx_fpga_attr.attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) pr_err("sysfs_create_file failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /* Maintainer: Alexander Clouter <alex@digriz.org.uk> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .atag_offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .nr_irqs = ORION5X_NR_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .init_machine = ts78xx_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .map_io = ts78xx_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .init_early = orion5x_init_early,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .init_irq = orion5x_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .init_time = orion5x_timer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .restart = orion5x_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) MACHINE_END
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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