^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * arch/arm/mach-orion5x/rd88f5182-setup.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Marvell Orion-NAS Reference Design Setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Maintainer: Ronen Shitrit <rshitrit@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mtd/physmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mv643xx_eth.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/ata_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/leds.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/mach/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "mpp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "orion5x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * RD-88F5182 Info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * 512K NOR flash Device bus boot chip select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RD88F5182_NOR_BOOT_BASE 0xf4000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RD88F5182_NOR_BOOT_SIZE SZ_512K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * 16M NOR flash on Device bus chip select 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RD88F5182_NOR_BASE 0xfc000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RD88F5182_NOR_SIZE SZ_16M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RD88F5182_PCI_SLOT0_OFFS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RD88F5182_PCI_SLOT0_IRQ_A_PIN 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RD88F5182_PCI_SLOT0_IRQ_B_PIN 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * 16M NOR Flash on Device bus CS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static struct physmap_flash_data rd88f5182_nor_flash_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static struct resource rd88f5182_nor_flash_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .start = RD88F5182_NOR_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .end = RD88F5182_NOR_BASE + RD88F5182_NOR_SIZE - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static struct platform_device rd88f5182_nor_flash = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .name = "physmap-flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .platform_data = &rd88f5182_nor_flash_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .num_resources = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .resource = &rd88f5182_nor_flash_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * Use GPIO LED as CPU active indication
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define RD88F5182_GPIO_LED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static struct gpio_led rd88f5182_gpio_led_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .name = "rd88f5182:cpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .default_trigger = "cpu0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .gpio = RD88F5182_GPIO_LED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static struct gpio_led_platform_data rd88f5182_gpio_led_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .leds = rd88f5182_gpio_led_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .num_leds = ARRAY_SIZE(rd88f5182_gpio_led_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static struct platform_device rd88f5182_gpio_leds = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .name = "leds-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .platform_data = &rd88f5182_gpio_led_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static void __init rd88f5182_pci_preinit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * Configure PCI GPIO IRQ pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (gpio_request(pin, "PCI IntA") == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (gpio_direction_input(pin) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) printk(KERN_ERR "rd88f5182_pci_preinit failed to "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) "set_irq_type pin %d\n", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) gpio_free(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (gpio_request(pin, "PCI IntB") == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (gpio_direction_input(pin) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) printk(KERN_ERR "rd88f5182_pci_preinit failed to "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) "set_irq_type pin %d\n", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) gpio_free(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) printk(KERN_ERR "rd88f5182_pci_preinit failed to gpio_request %d\n", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int __init rd88f5182_pci_map_irq(const struct pci_dev *dev, u8 slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * Check for devices with hard-wired IRQs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) irq = orion5x_pci_map_irq(dev, slot, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (irq != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * PCI IRQs are connected via GPIOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) switch (slot - RD88F5182_PCI_SLOT0_OFFS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (pin == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_A_PIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_B_PIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static struct hw_pci rd88f5182_pci __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .nr_controllers = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .preinit = rd88f5182_pci_preinit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .setup = orion5x_pci_sys_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .scan = orion5x_pci_sys_scan_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .map_irq = rd88f5182_pci_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int __init rd88f5182_pci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (machine_is_rd88f5182())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) pci_common_init(&rd88f5182_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) subsys_initcall(rd88f5182_pci_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * Ethernet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static struct mv643xx_eth_platform_data rd88f5182_eth_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .phy_addr = MV643XX_ETH_PHY_ADDR(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * RTC DS1338 on I2C bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static struct i2c_board_info __initdata rd88f5182_i2c_rtc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) I2C_BOARD_INFO("ds1338", 0x68),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * Sata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static struct mv_sata_platform_data rd88f5182_sata_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .n_ports = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * General Setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static unsigned int rd88f5182_mpp_modes[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) MPP0_GPIO, /* Debug Led */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) MPP1_GPIO, /* Reset Switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) MPP2_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) MPP3_GPIO, /* RTC Int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) MPP4_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) MPP5_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) MPP6_GPIO, /* PCI_intA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) MPP7_GPIO, /* PCI_intB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) MPP8_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) MPP9_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) MPP10_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) MPP11_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) MPP12_SATA_LED, /* SATA 0 presence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) MPP13_SATA_LED, /* SATA 1 presence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) MPP14_SATA_LED, /* SATA 0 active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) MPP15_SATA_LED, /* SATA 1 active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) MPP16_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) MPP17_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) MPP18_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) MPP19_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static void __init rd88f5182_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * Setup basic Orion functions. Need to be called early.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) orion5x_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) orion5x_mpp_conf(rd88f5182_mpp_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * MPP[20] PCI Clock to MV88F5182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * MPP[21] PCI Clock to mini PCI CON11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * MPP[22] USB 0 over current indication
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * MPP[23] USB 1 over current indication
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * MPP[24] USB 1 over current enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * MPP[25] USB 0 over current enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * Configure peripherals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) orion5x_ehci0_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) orion5x_ehci1_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) orion5x_eth_init(&rd88f5182_eth_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) orion5x_i2c_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) orion5x_sata_init(&rd88f5182_sata_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) orion5x_uart0_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) orion5x_xor_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ORION_MBUS_DEVBUS_BOOT_ATTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) RD88F5182_NOR_BOOT_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) RD88F5182_NOR_BOOT_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ORION_MBUS_DEVBUS_ATTR(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) RD88F5182_NOR_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) RD88F5182_NOR_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) platform_device_register(&rd88f5182_nor_flash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) platform_device_register(&rd88f5182_gpio_leds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .atag_offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .nr_irqs = ORION5X_NR_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .init_machine = rd88f5182_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .map_io = orion5x_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .init_early = orion5x_init_early,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .init_irq = orion5x_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .init_time = orion5x_timer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .restart = orion5x_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) MACHINE_END
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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