^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * arch/arm/mach-orion5x/pci.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * PCI and PCIe functions for Marvell Orion System On Chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mbus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <video/vga.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/mach/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <plat/pcie.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <plat/addr-map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "orion5x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Orion has one PCIe controller and one PCI controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Note1: The local PCIe bus number is '0'. The local PCI bus number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * follows the scanned PCIe bridged busses, if any.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Note2: It is possible for PCI/PCIe agents to access many subsystem's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * space, by configuring BARs and Address Decode Windows, e.g. flashes on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * device bus, Orion registers, etc. However this code only enable the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * access to DDR banks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * PCIe controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PCIE_BASE (ORION5X_PCIE_VIRT_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) void __init orion5x_pcie_id(u32 *dev, u32 *rev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *dev = orion_pcie_dev_id(PCIE_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *rev = orion_pcie_rev(PCIE_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static int pcie_valid_config(int bus, int dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Don't go out when trying to access --
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * 1. nonexisting device on local bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * 2. where there's no device connected (no link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (bus == 0 && dev == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (!orion_pcie_link_up(PCIE_BASE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (bus == 0 && dev != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * and then reading the PCIE_CONF_DATA register. Need to make sure these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * transactions are atomic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static DEFINE_SPINLOCK(orion5x_pcie_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) *val = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) spin_lock_irqsave(&orion5x_pcie_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int where, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) *val = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * We only support access to the non-extended configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * space when using the WA access method (or we would have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * sacrifice 256M of CPU virtual address space.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (where >= 0x100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) *val = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ret = orion_pcie_rd_conf_wa(ORION5X_PCIE_WA_VIRT_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) bus, devfn, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int where, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) spin_lock_irqsave(&orion5x_pcie_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static struct pci_ops pcie_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .read = pcie_rd_conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .write = pcie_wr_conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int __init pcie_setup(struct pci_sys_data *sys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * Generic PCIe unit setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) orion_pcie_setup(PCIE_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * Check whether to apply Orion-1/Orion-NAS PCIe config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * read transaction workaround.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) dev = orion_pcie_dev_id(PCIE_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "read transaction workaround\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_WA_TARGET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ORION_MBUS_PCIE_WA_ATTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ORION5X_PCIE_WA_PHYS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ORION5X_PCIE_WA_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) pcie_ops.read = pcie_rd_conf_wa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCIE_IO_PHYS_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * Request resources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) res = kzalloc(sizeof(struct resource), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) panic("pcie_setup unable to alloc resources");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * IORESOURCE_MEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) res->name = "PCIe Memory Space";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) res->flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) res->start = ORION5X_PCIE_MEM_PHYS_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) res->end = res->start + ORION5X_PCIE_MEM_SIZE - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (request_resource(&iomem_resource, res))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) panic("Request PCIe Memory resource failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * PCI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define PCI_MODE ORION5X_PCI_REG(0xd00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define PCI_CMD ORION5X_PCI_REG(0xc00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define PCI_CONF_ADDR ORION5X_PCI_REG(0xc78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define PCI_CONF_DATA ORION5X_PCI_REG(0xc7c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * PCI_MODE bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define PCI_MODE_64BIT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define PCI_MODE_PCIX ((1 << 4) | (1 << 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * PCI_CMD bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define PCI_CMD_HOST_REORDER (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * PCI_P2P_CONF bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define PCI_P2P_BUS_OFFS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define PCI_P2P_DEV_OFFS 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * PCI_CONF_ADDR bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define PCI_CONF_REG(reg) ((reg) & 0xfc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define PCI_CONF_FUNC(func) (((func) & 0x3) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define PCI_CONF_ADDR_EN (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * Internal configuration space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define PCI_CONF_FUNC_STAT_CMD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define PCI_CONF_REG_STAT_CMD 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define PCIX_STAT 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define PCIX_STAT_BUS_OFFS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * PCI Address Decode Windows registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * PCI configuration helpers for BAR settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * PCI config cycles are done by programming the PCI_CONF_ADDR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * and then reading the PCI_CONF_DATA register. Need to make sure these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * transactions are atomic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static DEFINE_SPINLOCK(orion5x_pci_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static int orion5x_pci_cardbus_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static int orion5x_pci_local_bus_nr(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u32 conf = readl(PCI_P2P_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u32 where, u32 size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) spin_lock_irqsave(&orion5x_pci_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) writel(PCI_CONF_BUS(bus) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) *val = readl(PCI_CONF_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) *val = (*val >> (8*(where & 0x3))) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) else if (size == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) *val = (*val >> (8*(where & 0x3))) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) spin_unlock_irqrestore(&orion5x_pci_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u32 where, u32 size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int ret = PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) spin_lock_irqsave(&orion5x_pci_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) writel(PCI_CONF_BUS(bus) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (size == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) __raw_writel(val, PCI_CONF_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) } else if (size == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) __raw_writew(val, PCI_CONF_DATA + (where & 0x3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) } else if (size == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) __raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ret = PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) spin_unlock_irqrestore(&orion5x_pci_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static int orion5x_pci_valid_config(int bus, u32 devfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (bus == orion5x_pci_local_bus_nr()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * Don't go out for local device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * When the PCI signals are directly connected to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * Cardbus slot, ignore all but device IDs 0 and 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (orion5x_pci_cardbus_mode && PCI_SLOT(devfn) > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) int where, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (!orion5x_pci_valid_config(bus->number, devfn)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) *val = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) PCI_FUNC(devfn), where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) int where, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (!orion5x_pci_valid_config(bus->number, devfn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) PCI_FUNC(devfn), where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static struct pci_ops pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .read = orion5x_pci_rd_conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .write = orion5x_pci_wr_conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static void __init orion5x_pci_set_bus_nr(int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u32 p2p = readl(PCI_P2P_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (readl(PCI_MODE) & PCI_MODE_PCIX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * PCI-X mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u32 pcix_status, bus, dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) pcix_status &= ~PCIX_STAT_BUS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) pcix_status |= (nr << PCIX_STAT_BUS_OFFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * PCI Conventional mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) p2p &= ~PCI_P2P_BUS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) p2p |= (nr << PCI_P2P_BUS_OFFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) writel(p2p, PCI_P2P_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static void __init orion5x_pci_master_slave_enable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) int bus_nr, func, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) bus_nr = orion5x_pci_local_bus_nr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) func = PCI_CONF_FUNC_STAT_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) reg = PCI_CONF_REG_STAT_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static void __init orion5x_setup_pci_wins(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) const struct mbus_dram_target_info *dram = mv_mbus_dram_info();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u32 win_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * First, disable windows.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) win_enable = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) writel(win_enable, PCI_BAR_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * Setup windows for DDR banks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) bus = orion5x_pci_local_bus_nr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) for (i = 0; i < dram->num_cs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) const struct mbus_dram_window *cs = dram->cs + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * Write DRAM bank base address register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) val = (cs->base & 0xfffff000) | (val & 0xfff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * Write DRAM bank size register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) writel((cs->size - 1) & 0xfffff000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) PCI_BAR_SIZE_DDR_CS(cs->cs_index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) writel(cs->base & 0xfffff000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) PCI_BAR_REMAP_DDR_CS(cs->cs_index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * Enable decode window for this chip select.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) win_enable &= ~(1 << cs->cs_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * Re-enable decode windows.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) writel(win_enable, PCI_BAR_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * Disable automatic update of address remapping when writing to BARs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static int __init pci_setup(struct pci_sys_data *sys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * Point PCI unit MBUS decode windows to DRAM space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) orion5x_setup_pci_wins();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * Master + Slave enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) orion5x_pci_master_slave_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * Force ordering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCI_IO_PHYS_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * Request resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) res = kzalloc(sizeof(struct resource), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) panic("pci_setup unable to alloc resources");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * IORESOURCE_MEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) res->name = "PCI Memory Space";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) res->flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) res->start = ORION5X_PCI_MEM_PHYS_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) res->end = res->start + ORION5X_PCI_MEM_SIZE - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (request_resource(&iomem_resource, res))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) panic("Request PCI Memory resource failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * General PCIe + PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static void rc_pci_fixup(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * Prevent enumeration of root complex.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (dev->bus->parent == NULL && dev->devfn == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) dev->resource[i].start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) dev->resource[i].end = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) dev->resource[i].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static int orion5x_pci_disabled __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) void __init orion5x_pci_disable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) orion5x_pci_disabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) void __init orion5x_pci_set_cardbus_mode(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) orion5x_pci_cardbus_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) vga_base = ORION5X_PCIE_MEM_PHYS_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (nr == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return pcie_setup(sys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (nr == 1 && !orion5x_pci_disabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) orion5x_pci_set_bus_nr(sys->busnr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return pci_setup(sys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) int __init orion5x_pci_sys_scan_bus(int nr, struct pci_host_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct pci_sys_data *sys = pci_host_bridge_priv(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) list_splice_init(&sys->resources, &bridge->windows);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) bridge->dev.parent = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) bridge->sysdata = sys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) bridge->busnr = sys->busnr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (nr == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) bridge->ops = &pcie_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return pci_scan_root_bus_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (nr == 1 && !orion5x_pci_disabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) bridge->ops = &pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return pci_scan_root_bus_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) int __init orion5x_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) int bus = dev->bus->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * PCIe endpoint?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (orion5x_pci_disabled || bus < orion5x_pci_local_bus_nr())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return IRQ_ORION5X_PCIE0_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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