^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __ARCH_ORION5X_MPP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __ARCH_ORION5X_MPP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #define MPP(_num, _sel, _in, _out, _F5181l, _F5182, _F5281) ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) /* MPP number */ ((_num) & 0xff) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) /* MPP select value */ (((_sel) & 0xf) << 8) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /* may be input signal */ ((!!(_in)) << 12) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* may be output signal */ ((!!(_out)) << 13) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* available on F5181l */ ((!!(_F5181l)) << 14) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* available on F5182 */ ((!!(_F5182)) << 15) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* available on F5281 */ ((!!(_F5281)) << 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* num sel i o 5181 5182 5281 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MPP_F5181_MASK MPP(0, 0x0, 0, 0, 1, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MPP_F5182_MASK MPP(0, 0x0, 0, 0, 0, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MPP_F5281_MASK MPP(0, 0x0, 0, 0, 0, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MPP0_UNUSED MPP(0, 0x3, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MPP0_GPIO MPP(0, 0x3, 1, 1, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MPP0_PCIE_RST_OUTn MPP(0, 0x0, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MPP0_PCI_ARB MPP(0, 0x2, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MPP1_UNUSED MPP(1, 0x0, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MPP1_GPIO MPP(1, 0x0, 1, 1, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MPP1_PCI_ARB MPP(1, 0x2, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MPP2_UNUSED MPP(2, 0x0, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MPP2_GPIO MPP(2, 0x0, 1, 1, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MPP2_PCI_ARB MPP(2, 0x2, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MPP2_PCI_PMEn MPP(2, 0x3, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MPP3_UNUSED MPP(3, 0x0, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MPP3_GPIO MPP(3, 0x0, 1, 1, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MPP3_PCI_ARB MPP(3, 0x2, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MPP4_UNUSED MPP(4, 0x0, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MPP4_GPIO MPP(4, 0x0, 1, 1, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MPP4_PCI_ARB MPP(4, 0x2, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MPP4_NAND MPP(4, 0x4, 0, 0, 0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MPP4_SATA_LED MPP(4, 0x5, 0, 0, 0, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MPP5_UNUSED MPP(5, 0x0, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MPP5_GPIO MPP(5, 0x0, 1, 1, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MPP5_PCI_ARB MPP(5, 0x2, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MPP5_NAND MPP(5, 0x4, 0, 0, 0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MPP5_SATA_LED MPP(5, 0x5, 0, 0, 0, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MPP6_UNUSED MPP(6, 0x0, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MPP6_GPIO MPP(6, 0x0, 1, 1, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MPP6_PCI_ARB MPP(6, 0x2, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MPP6_NAND MPP(6, 0x4, 0, 0, 0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MPP6_PCI_CLK MPP(6, 0x5, 0, 0, 1, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MPP6_SATA_LED MPP(6, 0x5, 0, 0, 0, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MPP7_UNUSED MPP(7, 0x0, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MPP7_GPIO MPP(7, 0x0, 1, 1, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MPP7_PCI_ARB MPP(7, 0x2, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MPP7_NAND MPP(7, 0x4, 0, 0, 0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MPP7_PCI_CLK MPP(7, 0x5, 0, 0, 1, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MPP7_SATA_LED MPP(7, 0x5, 0, 0, 0, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MPP8_UNUSED MPP(8, 0x0, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MPP8_GPIO MPP(8, 0x0, 1, 1, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MPP8_GIGE MPP(8, 0x1, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MPP9_UNUSED MPP(9, 0x0, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MPP9_GPIO MPP(9, 0x0, 1, 1, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MPP9_GIGE MPP(9, 0x1, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MPP10_UNUSED MPP(10, 0x0, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MPP10_GPIO MPP(10, 0x0, 1, 1, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MPP10_GIGE MPP(10, 0x1, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MPP11_UNUSED MPP(11, 0x0, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MPP11_GPIO MPP(11, 0x0, 1, 1, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MPP11_GIGE MPP(11, 0x1, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MPP12_UNUSED MPP(12, 0x0, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MPP12_GPIO MPP(12, 0x0, 1, 1, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MPP12_GIGE MPP(12, 0x1, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MPP12_NAND MPP(12, 0x4, 0, 0, 0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MPP12_SATA_LED MPP(12, 0x5, 0, 0, 0, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MPP13_UNUSED MPP(13, 0x0, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MPP13_GPIO MPP(13, 0x0, 1, 1, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MPP13_GIGE MPP(13, 0x1, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MPP13_NAND MPP(13, 0x4, 0, 0, 0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MPP13_SATA_LED MPP(13, 0x5, 0, 0, 0, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MPP14_UNUSED MPP(14, 0x0, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MPP14_GPIO MPP(14, 0x0, 1, 1, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MPP14_GIGE MPP(14, 0x1, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MPP14_NAND MPP(14, 0x4, 0, 0, 0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MPP14_SATA_LED MPP(14, 0x5, 0, 0, 0, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MPP15_UNUSED MPP(15, 0x0, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MPP15_GPIO MPP(15, 0x0, 1, 1, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MPP15_GIGE MPP(15, 0x1, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MPP15_NAND MPP(15, 0x4, 0, 0, 0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MPP15_SATA_LED MPP(15, 0x5, 0, 0, 0, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MPP16_UNUSED MPP(16, 0x0, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MPP16_GPIO MPP(16, 0x5, 1, 1, 0, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MPP16_GIGE MPP(16, 0x1, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MPP16_NAND MPP(16, 0x4, 0, 0, 0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MPP16_UART MPP(16, 0x0, 0, 0, 0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MPP17_UNUSED MPP(17, 0x0, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MPP17_GPIO MPP(17, 0x5, 1, 1, 0, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MPP17_GIGE MPP(17, 0x1, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MPP17_NAND MPP(17, 0x4, 0, 0, 0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MPP17_UART MPP(17, 0x0, 0, 0, 0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MPP18_UNUSED MPP(18, 0x0, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MPP18_GPIO MPP(18, 0x5, 1, 1, 0, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MPP18_GIGE MPP(18, 0x1, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MPP18_UART MPP(18, 0x0, 0, 0, 0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MPP19_UNUSED MPP(19, 0x0, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MPP19_GPIO MPP(19, 0x5, 1, 1, 0, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MPP19_GIGE MPP(19, 0x1, 0, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MPP19_UART MPP(19, 0x0, 0, 0, 0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MPP_MAX 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) void orion5x_mpp_conf(unsigned int *mpp_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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