^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * arch/arm/mach-orion5x/db88f5281-setup.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Marvell Orion-2 Development Board Setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mtd/physmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mtd/rawnand.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mv643xx_eth.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/mach/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/platform_data/mtd-orion_nand.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "mpp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "orion5x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * DB-88F5281 on board devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * 512K NOR flash Device bus boot chip select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DB88F5281_NOR_BOOT_BASE 0xf4000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DB88F5281_NOR_BOOT_SIZE SZ_512K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * 7-Segment on Device bus chip select 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DB88F5281_7SEG_BASE 0xfa000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DB88F5281_7SEG_SIZE SZ_1K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * 32M NOR flash on Device bus chip select 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DB88F5281_NOR_BASE 0xfc000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DB88F5281_NOR_SIZE SZ_32M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * 32M NAND flash on Device bus chip select 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DB88F5281_NAND_BASE 0xfa800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DB88F5281_NAND_SIZE SZ_1K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DB88F5281_PCI_SLOT0_OFFS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DB88F5281_PCI_SLOT0_IRQ_PIN 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * 512M NOR Flash on Device bus Boot CS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static struct physmap_flash_data db88f5281_boot_flash_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .width = 1, /* 8 bit bus width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static struct resource db88f5281_boot_flash_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .start = DB88F5281_NOR_BOOT_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .end = DB88F5281_NOR_BOOT_BASE + DB88F5281_NOR_BOOT_SIZE - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static struct platform_device db88f5281_boot_flash = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .name = "physmap-flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .platform_data = &db88f5281_boot_flash_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .num_resources = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .resource = &db88f5281_boot_flash_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * 32M NOR Flash on Device bus CS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static struct physmap_flash_data db88f5281_nor_flash_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .width = 4, /* 32 bit bus width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static struct resource db88f5281_nor_flash_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .start = DB88F5281_NOR_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .end = DB88F5281_NOR_BASE + DB88F5281_NOR_SIZE - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static struct platform_device db88f5281_nor_flash = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .name = "physmap-flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .platform_data = &db88f5281_nor_flash_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .num_resources = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .resource = &db88f5281_nor_flash_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * 32M NAND Flash on Device bus CS2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static struct mtd_partition db88f5281_nand_parts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .name = "kernel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .size = SZ_2M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .name = "root",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .offset = SZ_2M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .size = (SZ_16M - SZ_2M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .name = "user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .offset = SZ_16M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .size = SZ_8M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .name = "recovery",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .offset = (SZ_16M + SZ_8M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .size = SZ_8M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static struct resource db88f5281_nand_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .start = DB88F5281_NAND_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .end = DB88F5281_NAND_BASE + DB88F5281_NAND_SIZE - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static struct orion_nand_data db88f5281_nand_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .parts = db88f5281_nand_parts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .nr_parts = ARRAY_SIZE(db88f5281_nand_parts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .cle = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .ale = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static struct platform_device db88f5281_nand_flash = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .name = "orion_nand",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .platform_data = &db88f5281_nand_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .resource = &db88f5281_nand_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .num_resources = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * 7-Segment on Device bus CS0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * Dummy counter every 2 sec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static void __iomem *db88f5281_7seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static struct timer_list db88f5281_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static void db88f5281_7seg_event(struct timer_list *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) writel(0, db88f5281_7seg + (count << 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) count = (count + 1) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) mod_timer(&db88f5281_timer, jiffies + 2 * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int __init db88f5281_7seg_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (machine_is_db88f5281()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) db88f5281_7seg = ioremap(DB88F5281_7SEG_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) DB88F5281_7SEG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (!db88f5281_7seg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) printk(KERN_ERR "Failed to ioremap db88f5281_7seg\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) timer_setup(&db88f5281_timer, db88f5281_7seg_event, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) mod_timer(&db88f5281_timer, jiffies + 2 * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) __initcall(db88f5281_7seg_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static void __init db88f5281_pci_preinit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * Configure PCI GPIO IRQ pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) pin = DB88F5281_PCI_SLOT0_IRQ_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (gpio_request(pin, "PCI Int1") == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (gpio_direction_input(pin) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) printk(KERN_ERR "db88f5281_pci_preinit failed to "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) "set_irq_type pin %d\n", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) gpio_free(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (gpio_request(pin, "PCI Int2") == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (gpio_direction_input(pin) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) printk(KERN_ERR "db88f5281_pci_preinit failed "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) "to set_irq_type pin %d\n", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) gpio_free(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int __init db88f5281_pci_map_irq(const struct pci_dev *dev, u8 slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * Check for devices with hard-wired IRQs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) irq = orion5x_pci_map_irq(dev, slot, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (irq != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * PCI IRQs are connected via GPIOs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) switch (slot - DB88F5281_PCI_SLOT0_OFFS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return gpio_to_irq(DB88F5281_PCI_SLOT0_IRQ_PIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return gpio_to_irq(DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static struct hw_pci db88f5281_pci __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .nr_controllers = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .preinit = db88f5281_pci_preinit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .setup = orion5x_pci_sys_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .scan = orion5x_pci_sys_scan_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .map_irq = db88f5281_pci_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static int __init db88f5281_pci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (machine_is_db88f5281())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) pci_common_init(&db88f5281_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) subsys_initcall(db88f5281_pci_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * Ethernet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static struct mv643xx_eth_platform_data db88f5281_eth_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .phy_addr = MV643XX_ETH_PHY_ADDR(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * RTC DS1339 on I2C bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static struct i2c_board_info __initdata db88f5281_i2c_rtc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) I2C_BOARD_INFO("ds1339", 0x68),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * General Setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static unsigned int db88f5281_mpp_modes[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) MPP0_GPIO, /* USB Over Current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) MPP1_GPIO, /* USB Vbat input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) MPP2_PCI_ARB, /* PCI_REQn[2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MPP3_PCI_ARB, /* PCI_GNTn[2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) MPP4_PCI_ARB, /* PCI_REQn[3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) MPP5_PCI_ARB, /* PCI_GNTn[3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) MPP6_GPIO, /* JP0, CON17.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) MPP7_GPIO, /* JP1, CON17.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) MPP8_GPIO, /* JP2, CON11.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) MPP9_GPIO, /* JP3, CON11.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) MPP10_GPIO, /* RTC int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) MPP11_GPIO, /* Baud Rate Generator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) MPP12_GPIO, /* PCI int 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) MPP13_GPIO, /* PCI int 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) MPP14_NAND, /* NAND_REn[2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) MPP15_NAND, /* NAND_WEn[2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) MPP16_UART, /* UART1_RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) MPP17_UART, /* UART1_TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) MPP18_UART, /* UART1_CTSn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) MPP19_UART, /* UART1_RTSn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static void __init db88f5281_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * Basic Orion setup. Need to be called early.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) orion5x_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) orion5x_mpp_conf(db88f5281_mpp_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * Configure peripherals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) orion5x_ehci0_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) orion5x_eth_init(&db88f5281_eth_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) orion5x_i2c_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) orion5x_uart0_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) orion5x_uart1_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ORION_MBUS_DEVBUS_BOOT_ATTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) DB88F5281_NOR_BOOT_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) DB88F5281_NOR_BOOT_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) platform_device_register(&db88f5281_boot_flash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ORION_MBUS_DEVBUS_ATTR(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) DB88F5281_7SEG_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) DB88F5281_7SEG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ORION_MBUS_DEVBUS_ATTR(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) DB88F5281_NOR_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) DB88F5281_NOR_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) platform_device_register(&db88f5281_nor_flash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ORION_MBUS_DEVBUS_ATTR(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) DB88F5281_NAND_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) DB88F5281_NAND_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) platform_device_register(&db88f5281_nand_flash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) i2c_register_board_info(0, &db88f5281_i2c_rtc, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .atag_offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .nr_irqs = ORION5X_NR_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .init_machine = db88f5281_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .map_io = orion5x_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .init_early = orion5x_init_early,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .init_irq = orion5x_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .init_time = orion5x_timer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .restart = orion5x_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) MACHINE_END
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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