Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * arch/arm/mach-orion5x/common.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Core functions for Marvell Orion 5x SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * License version 2.  This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/serial_8250.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/mv643xx_i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/ata_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/platform_data/dsa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <asm/system_misc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <asm/mach/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <linux/platform_data/mtd-orion_nand.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <linux/platform_data/usb-ehci-orion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <plat/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include <plat/common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #include "bridge-regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #include "orion5x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * I/O Address Mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) static struct map_desc orion5x_io_desc[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		.virtual	= (unsigned long) ORION5X_REGS_VIRT_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		.pfn		= __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		.length		= ORION5X_REGS_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		.type		= MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		.virtual	= (unsigned long) ORION5X_PCIE_WA_VIRT_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		.pfn		= __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		.length		= ORION5X_PCIE_WA_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		.type		= MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) void __init orion5x_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  * CLK tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) static struct clk *tclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) void __init clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, orion5x_tclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	orion_clkdev_init(tclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  * EHCI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) void __init orion5x_ehci0_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 			EHCI_PHY_ORION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  * EHCI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)  ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) void __init orion5x_ehci1_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	orion_ehci_1_init(ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)  * GE00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96)  ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	orion_ge00_init(eth_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 			ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			IRQ_ORION5X_ETH_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 			MV643XX_TX_CSUM_DEFAULT_LIMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)  * Ethernet switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)  ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) void __init orion5x_eth_switch_init(struct dsa_chip_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	orion_ge00_switch_init(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)  * I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)  ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) void __init orion5x_i2c_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)  * SATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	orion_sata_init(sata_data, ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)  * SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)  ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) void __init orion5x_spi_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	orion_spi_init(SPI_PHYS_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)  * UART0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) void __init orion5x_uart0_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			 IRQ_ORION5X_UART0, tclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)  * UART1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)  ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) void __init orion5x_uart1_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			 IRQ_ORION5X_UART1, tclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)  * XOR engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)  ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) void __init orion5x_xor_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	orion_xor0_init(ORION5X_XOR_PHYS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			ORION5X_XOR_PHYS_BASE + 0x200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 			IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)  * Cryptographic Engines and Security Accelerator (CESA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)  ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static void __init orion5x_crypto_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	mvebu_mbus_add_window_by_id(ORION_MBUS_SRAM_TARGET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 				    ORION_MBUS_SRAM_ATTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 				    ORION5X_SRAM_PHYS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 				    ORION5X_SRAM_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			  SZ_8K, IRQ_ORION5X_CESA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)  * Watchdog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)  ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static struct resource orion_wdt_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		DEFINE_RES_MEM(RSTOUTn_MASK_PHYS, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static struct platform_device orion_wdt_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	.name		= "orion_wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	.id		= -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	.num_resources	= ARRAY_SIZE(orion_wdt_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	.resource	= orion_wdt_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static void __init orion5x_wdt_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	platform_device_register(&orion_wdt_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)  * Time handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)  ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) void __init orion5x_init_early(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	u32 rev, dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	const char *mbus_soc_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	orion_time_set_base(TIMER_VIRT_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	/* Initialize the MBUS driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	orion5x_pcie_id(&dev, &rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	if (dev == MV88F5281_DEV_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		mbus_soc_name = "marvell,orion5x-88f5281-mbus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	else if (dev == MV88F5182_DEV_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		mbus_soc_name = "marvell,orion5x-88f5182-mbus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	else if (dev == MV88F5181_DEV_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		mbus_soc_name = "marvell,orion5x-88f5181-mbus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	else if (dev == MV88F6183_DEV_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		mbus_soc_name = "marvell,orion5x-88f6183-mbus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		mbus_soc_name = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	mvebu_mbus_init(mbus_soc_name, ORION5X_BRIDGE_WINS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			ORION5X_BRIDGE_WINS_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 			ORION5X_DDR_WINS_BASE, ORION5X_DDR_WINS_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) void orion5x_setup_wins(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	 * The PCIe windows will no longer be statically allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	 * here once Orion5x is migrated to the pci-mvebu driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCIE_IO_TARGET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 					  ORION_MBUS_PCIE_IO_ATTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 					  ORION5X_PCIE_IO_PHYS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 					  ORION5X_PCIE_IO_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 					  ORION5X_PCIE_IO_BUS_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_MEM_TARGET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 				    ORION_MBUS_PCIE_MEM_ATTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 				    ORION5X_PCIE_MEM_PHYS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 				    ORION5X_PCIE_MEM_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 					  ORION_MBUS_PCI_IO_ATTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 					  ORION5X_PCI_IO_PHYS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 					  ORION5X_PCI_IO_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 					  ORION5X_PCI_IO_BUS_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 				    ORION_MBUS_PCI_MEM_ATTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 				    ORION5X_PCI_MEM_PHYS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 				    ORION5X_PCI_MEM_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) int orion5x_tclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static int __init orion5x_find_tclk(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	u32 dev, rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	orion5x_pcie_id(&dev, &rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	if (dev == MV88F6183_DEV_ID &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	    (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		return 133333333;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	return 166666667;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) void __init orion5x_timer_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	orion5x_tclk = orion5x_find_tclk();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 			IRQ_ORION5X_BRIDGE, orion5x_tclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)  * General
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)  ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)  * Identify device ID and rev from PCIe configuration header space '0'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	orion5x_pcie_id(dev, rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	if (*dev == MV88F5281_DEV_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		if (*rev == MV88F5281_REV_D2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 			*dev_name = "MV88F5281-D2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		} else if (*rev == MV88F5281_REV_D1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 			*dev_name = "MV88F5281-D1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		} else if (*rev == MV88F5281_REV_D0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 			*dev_name = "MV88F5281-D0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 			*dev_name = "MV88F5281-Rev-Unsupported";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	} else if (*dev == MV88F5182_DEV_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		if (*rev == MV88F5182_REV_A2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 			*dev_name = "MV88F5182-A2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			*dev_name = "MV88F5182-Rev-Unsupported";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	} else if (*dev == MV88F5181_DEV_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		if (*rev == MV88F5181_REV_B1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 			*dev_name = "MV88F5181-Rev-B1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		} else if (*rev == MV88F5181L_REV_A1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 			*dev_name = "MV88F5181L-Rev-A1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 			*dev_name = "MV88F5181(L)-Rev-Unsupported";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	} else if (*dev == MV88F6183_DEV_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		if (*rev == MV88F6183_REV_B0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 			*dev_name = "MV88F6183-Rev-B0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 			*dev_name = "MV88F6183-Rev-Unsupported";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		*dev_name = "Device-Unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) void __init orion5x_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	char *dev_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	u32 dev, rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	orion5x_id(&dev, &rev, &dev_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	 * Setup Orion address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	orion5x_setup_wins();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	/* Setup root of clk tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	clk_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	 * Don't issue "Wait for Interrupt" instruction if we are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	 * running on D0 5281 silicon.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		cpu_idle_poll_ctrl(true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	 * The 5082/5181l/5182/6082/6082l/6183 have crypto
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	 * while 5180n/5181/5281 don't have crypto.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	    dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		orion5x_crypto_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	 * Register watchdog driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	orion5x_wdt_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) void orion5x_restart(enum reboot_mode mode, const char *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	 * Enable and issue soft reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	orion5x_setbits(RSTOUTn_MASK, (1 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	orion5x_setbits(CPU_SOFT_RESET, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	mdelay(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	orion5x_clrbits(CPU_SOFT_RESET, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)  * Many orion-based systems have buggy bootloader implementations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)  * This is a common fixup for bogus memory tags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) void __init tag_fixup_mem32(struct tag *t, char **from)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	for (; t->hdr.size; t = tag_next(t))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		if (t->hdr.tag == ATAG_MEM &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		    (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		     t->u.mem.start & ~PAGE_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 			printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 			       "Clearing invalid memory bank %dKB@0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 			       t->u.mem.size / 1024, t->u.mem.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 			t->hdr.tag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }