^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * arch/arm/mach-orion5x/rd88f5182-setup.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Marvell Orion-NAS Reference Design Setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Maintainer: Ronen Shitrit <rshitrit@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/mach/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "orion5x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * RD-88F5182 Info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RD88F5182_PCI_SLOT0_OFFS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RD88F5182_PCI_SLOT0_IRQ_A_PIN 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RD88F5182_PCI_SLOT0_IRQ_B_PIN 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static void __init rd88f5182_pci_preinit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) int pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Configure PCI GPIO IRQ pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (gpio_request(pin, "PCI IntA") == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (gpio_direction_input(pin) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) printk(KERN_ERR "rd88f5182_pci_preinit failed to "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) "set_irq_type pin %d\n", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) gpio_free(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (gpio_request(pin, "PCI IntB") == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (gpio_direction_input(pin) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) printk(KERN_ERR "rd88f5182_pci_preinit failed to "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "set_irq_type pin %d\n", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) gpio_free(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) printk(KERN_ERR "rd88f5182_pci_preinit failed to gpio_request %d\n", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int __init rd88f5182_pci_map_irq(const struct pci_dev *dev, u8 slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * Check for devices with hard-wired IRQs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) irq = orion5x_pci_map_irq(dev, slot, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (irq != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * PCI IRQs are connected via GPIOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) switch (slot - RD88F5182_PCI_SLOT0_OFFS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (pin == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_A_PIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_B_PIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static struct hw_pci rd88f5182_pci __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .nr_controllers = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .preinit = rd88f5182_pci_preinit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .setup = orion5x_pci_sys_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .scan = orion5x_pci_sys_scan_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .map_irq = rd88f5182_pci_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int __init rd88f5182_pci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (of_machine_is_compatible("marvell,rd-88f5182-nas"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) pci_common_init(&rd88f5182_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) subsys_initcall(rd88f5182_pci_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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