^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Maxtor Shared Storage II Board Setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Maintainer: Sylver Bruneau <sylver.bruneau@googlemail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/mach/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "orion5x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "bridge-regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Maxtor Shared Storage II Info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * PCI setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static int __init mss2_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Check for devices with hard-wired IRQs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) irq = orion5x_pci_map_irq(dev, slot, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) if (irq != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static struct hw_pci mss2_pci __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .nr_controllers = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .setup = orion5x_pci_sys_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .scan = orion5x_pci_sys_scan_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .map_irq = mss2_pci_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static int __init mss2_pci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (machine_is_mss2())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) pci_common_init(&mss2_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) subsys_initcall(mss2_pci_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * MSS2 power off method
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * On the Maxtor Shared Storage II, the shutdown process is the following :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * - Userland modifies U-boot env to tell U-boot to go idle at next boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * - The board reboots
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * - U-boot starts and go into an idle mode until the user press "power"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static void mss2_power_off(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * Enable and issue soft reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) reg = readl(RSTOUTn_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) reg |= 1 << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) writel(reg, RSTOUTn_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) reg = readl(CPU_SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) reg |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) writel(reg, CPU_SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) void __init mss2_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* register mss2 specific power-off method */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) pm_power_off = mss2_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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