^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP3/4 Voltage Controller (VC) structure and macro definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007, 2010 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Rajendra Nayak <rnayak@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Lesly A M <x0080970@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Thara Gopinath <thara@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2008, 2011 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Kalle Jokiniemi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Paul Walmsley
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #ifndef __ARCH_ARM_MACH_OMAP2_VC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define __ARCH_ARM_MACH_OMAP2_VC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct voltagedomain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * struct omap_vc_common - per-VC register/bitfield data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * @cmd_on_mask: ON bitmask in PRM_VC_CMD_VAL* register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * @valid: VALID bitmask in PRM_VC_BYPASS_VAL register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * @bypass_val_reg: Offset of PRM_VC_BYPASS_VAL reg from PRM start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * @data_shift: DATA field shift in PRM_VC_BYPASS_VAL register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * @slaveaddr_shift: SLAVEADDR field shift in PRM_VC_BYPASS_VAL register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * @regaddr_shift: REGADDR field shift in PRM_VC_BYPASS_VAL register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * @cmd_on_shift: ON field shift in PRM_VC_CMD_VAL_* register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * @cmd_onlp_shift: ONLP field shift in PRM_VC_CMD_VAL_* register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * @cmd_ret_shift: RET field shift in PRM_VC_CMD_VAL_* register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * @cmd_off_shift: OFF field shift in PRM_VC_CMD_VAL_* register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * @i2c_cfg_reg: I2C configuration register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * @i2c_cfg_clear_mask: high-speed mode bit clear mask in I2C config register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * @i2c_cfg_hsen_mask: high-speed mode bit field mask in I2C config register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * @i2c_mcode_mask: MCODE field mask for I2C config register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * XXX One of cmd_on_mask and cmd_on_shift are not needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * XXX VALID should probably be a shift, not a mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct omap_vc_common {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 cmd_on_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u8 bypass_val_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u8 data_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u8 slaveaddr_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u8 regaddr_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u8 cmd_on_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u8 cmd_onlp_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u8 cmd_ret_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u8 cmd_off_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u8 i2c_cfg_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u8 i2c_cfg_clear_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u8 i2c_cfg_hsen_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u8 i2c_mcode_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* omap_vc_channel.flags values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OMAP_VC_CHANNEL_DEFAULT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OMAP_VC_CHANNEL_CFG_MUTANT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * struct omap_vc_channel - VC per-instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * @i2c_slave_addr: I2C slave address of PMIC for this VC channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * @volt_reg_addr: voltage configuration register address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * @cmd_reg_addr: command configuration register address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @setup_time: setup time (in sys_clk cycles) of regulator for this channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * @cfg_channel: current value of VC channel configuration register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * @i2c_high_speed: whether or not to use I2C high-speed mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * @common: pointer to VC common data for this platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * @smps_sa_mask: i2c slave address bitmask in the PRM_VC_SMPS_SA register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * @smps_volra_mask: VOLRA* bitmask in the PRM_VC_VOL_RA register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * @smps_cmdra_mask: CMDRA* bitmask in the PRM_VC_CMD_RA register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * @cmdval_reg: register for on/ret/off voltage level values for this channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * @smps_sa_reg: Offset of PRM_VC_SMPS_SA reg from PRM start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * @smps_volra_reg: Offset of PRM_VC_SMPS_VOL_RA reg from PRM start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * @smps_cmdra_reg: Offset of PRM_VC_SMPS_CMD_RA reg from PRM start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * @cfg_channel_reg: VC channel configuration register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * @cfg_channel_sa_shift: bit shift for slave address cfg_channel register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * @flags: VC channel-specific flags (optional)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct omap_vc_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* channel state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u16 i2c_slave_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u16 volt_reg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u16 cmd_reg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u8 cfg_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) bool i2c_high_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* register access data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) const struct omap_vc_common *common;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 smps_sa_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 smps_volra_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 smps_cmdra_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u8 cmdval_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u8 smps_sa_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u8 smps_volra_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u8 smps_cmdra_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u8 cfg_channel_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u8 cfg_channel_sa_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) extern struct omap_vc_channel omap3_vc_mpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) extern struct omap_vc_channel omap3_vc_core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) extern struct omap_vc_channel omap4_vc_mpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) extern struct omap_vc_channel omap4_vc_iva;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) extern struct omap_vc_channel omap4_vc_core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) extern struct omap_vc_param omap3_mpu_vc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) extern struct omap_vc_param omap3_core_vc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) extern struct omap_vc_param omap4_mpu_vc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) extern struct omap_vc_param omap4_iva_vc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) extern struct omap_vc_param omap4_core_vc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) void omap3_vc_set_pmic_signaling(int core_next_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) void omap4_vc_set_pmic_signaling(int core_next_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) void omap_vc_init_channel(struct voltagedomain *voltdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int omap_vc_pre_scale(struct voltagedomain *voltdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned long target_volt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u8 *target_vsel, u8 *current_vsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) void omap_vc_post_scale(struct voltagedomain *voltdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned long target_volt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u8 target_vsel, u8 current_vsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int omap_vc_bypass_scale(struct voltagedomain *voltdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned long target_volt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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