^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * OMAP Voltage Controller (VC) interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2011 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "iomap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "voltage.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "vc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "prm-regbits-34xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "prm-regbits-44xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "prm44xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "pm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "scrm44xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "control.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define OMAP4430_VDD_IVA_I2C_DISABLE BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define OMAP4430_VDD_MPU_I2C_DISABLE BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OMAP4430_VDD_CORE_I2C_DISABLE BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OMAP4430_VDD_IVA_PRESENCE BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OMAP4430_VDD_MPU_PRESENCE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OMAP4430_AUTO_CTRL_VDD_IVA(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OMAP4430_AUTO_CTRL_VDD_MPU(x) ((x) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OMAP4430_AUTO_CTRL_VDD_CORE(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OMAP4430_AUTO_CTRL_VDD_RET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OMAP4430_VDD_I2C_DISABLE_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) (OMAP4430_VDD_IVA_I2C_DISABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) OMAP4430_VDD_MPU_I2C_DISABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) OMAP4430_VDD_CORE_I2C_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OMAP4_VDD_DEFAULT_VAL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) (OMAP4430_VDD_I2C_DISABLE_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) OMAP4430_VDD_IVA_PRESENCE | OMAP4430_VDD_MPU_PRESENCE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) OMAP4430_AUTO_CTRL_VDD_IVA(OMAP4430_AUTO_CTRL_VDD_RET) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) OMAP4430_AUTO_CTRL_VDD_MPU(OMAP4430_AUTO_CTRL_VDD_RET) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) OMAP4430_AUTO_CTRL_VDD_CORE(OMAP4430_AUTO_CTRL_VDD_RET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OMAP4_VDD_RET_VAL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) (OMAP4_VDD_DEFAULT_VAL & ~OMAP4430_VDD_I2C_DISABLE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * struct omap_vc_channel_cfg - describe the cfg_channel bitfield
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @sa: bit for slave address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @rav: bit for voltage configuration register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @rac: bit for command configuration register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @racen: enable bit for RAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @cmd: bit for command value set selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * Channel configuration bits, common for OMAP3+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * OMAP3 register: PRM_VC_CH_CONF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * OMAP4 register: PRM_VC_CFG_CHANNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * OMAP5 register: PRM_VC_SMPS_<voltdm>_CONFIG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct omap_vc_channel_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u8 sa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u8 rav;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u8 rac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u8 racen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u8 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static struct omap_vc_channel_cfg vc_default_channel_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .sa = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .rav = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .rac = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .racen = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .cmd = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * On OMAP3+, all VC channels have the above default bitfield
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * configuration, except the OMAP4 MPU channel. This appears
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * to be a freak accident as every other VC channel has the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * default configuration, thus creating a mutant channel config.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static struct omap_vc_channel_cfg vc_mutant_channel_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .sa = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .rav = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .rac = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .racen = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .cmd = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static struct omap_vc_channel_cfg *vc_cfg_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* Default I2C trace length on pcb, 6.3cm. Used for capacitance calculations. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static u32 sr_i2c_pcb_length = 63;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CFG_CHANNEL_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * omap_vc_config_channel - configure VC channel to PMIC mappings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * @voltdm: pointer to voltagdomain defining the desired VC channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * Configures the VC channel to PMIC mappings for the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * PMIC settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * - i2c slave address (SA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * - voltage configuration address (RAV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * - command configuration address (RAC) and enable bit (RACEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * - command values for ON, ONLP, RET and OFF (CMD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * This function currently only allows flexible configuration of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * non-default channel. Starting with OMAP4, there are more than 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * channels, with one defined as the default (on OMAP4, it's MPU.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * Only the non-default channel can be configured.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int omap_vc_config_channel(struct voltagedomain *voltdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct omap_vc_channel *vc = voltdm->vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * For default channel, the only configurable bit is RACEN.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * All others must stay at zero (see function comment above.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (vc->flags & OMAP_VC_CHANNEL_DEFAULT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) vc->cfg_channel &= vc_cfg_bits->racen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) voltdm->rmw(CFG_CHANNEL_MASK << vc->cfg_channel_sa_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) vc->cfg_channel << vc->cfg_channel_sa_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) vc->cfg_channel_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Voltage scale and accessory APIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int omap_vc_pre_scale(struct voltagedomain *voltdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned long target_volt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u8 *target_vsel, u8 *current_vsel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct omap_vc_channel *vc = voltdm->vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 vc_cmdval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Check if sufficient pmic info is available for this vdd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (!voltdm->pmic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) pr_err("%s: Insufficient pmic info to scale the vdd_%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) __func__, voltdm->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (!voltdm->pmic->uv_to_vsel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) pr_err("%s: PMIC function to convert voltage in uV to vsel not registered. Hence unable to scale voltage for vdd_%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) __func__, voltdm->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (!voltdm->read || !voltdm->write) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) pr_err("%s: No read/write API for accessing vdd_%s regs\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) __func__, voltdm->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) *target_vsel = voltdm->pmic->uv_to_vsel(target_volt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) *current_vsel = voltdm->pmic->uv_to_vsel(voltdm->nominal_volt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Setting the ON voltage to the new target voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) vc_cmdval = voltdm->read(vc->cmdval_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) vc_cmdval &= ~vc->common->cmd_on_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) vc_cmdval |= (*target_vsel << vc->common->cmd_on_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) voltdm->write(vc_cmdval, vc->cmdval_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) voltdm->vc_param->on = target_volt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) omap_vp_update_errorgain(voltdm, target_volt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) void omap_vc_post_scale(struct voltagedomain *voltdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned long target_volt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u8 target_vsel, u8 current_vsel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 smps_steps = 0, smps_delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) smps_steps = abs(target_vsel - current_vsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* SMPS slew rate / step size. 2us added as buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) smps_delay = ((smps_steps * voltdm->pmic->step_size) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) voltdm->pmic->slew_rate) + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) udelay(smps_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* vc_bypass_scale - VC bypass method of voltage scaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int omap_vc_bypass_scale(struct voltagedomain *voltdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned long target_volt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct omap_vc_channel *vc = voltdm->vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u32 loop_cnt = 0, retries_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u32 vc_valid, vc_bypass_val_reg, vc_bypass_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u8 target_vsel, current_vsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, ¤t_vsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) vc_valid = vc->common->valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) vc_bypass_val_reg = vc->common->bypass_val_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) vc_bypass_value = (target_vsel << vc->common->data_shift) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) (vc->volt_reg_addr << vc->common->regaddr_shift) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) (vc->i2c_slave_addr << vc->common->slaveaddr_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) voltdm->write(vc_bypass_value, vc_bypass_val_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) voltdm->write(vc_bypass_value | vc_valid, vc_bypass_val_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) vc_bypass_value = voltdm->read(vc_bypass_val_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * Loop till the bypass command is acknowledged from the SMPS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * NOTE: This is legacy code. The loop count and retry count needs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * to be revisited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) while (!(vc_bypass_value & vc_valid)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) loop_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (retries_cnt > 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) pr_warn("%s: Retry count exceeded\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (loop_cnt > 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) retries_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) loop_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) vc_bypass_value = voltdm->read(vc_bypass_val_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* Convert microsecond value to number of 32kHz clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static inline u32 omap_usec_to_32k(u32 usec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return DIV_ROUND_UP_ULL(32768ULL * (u64)usec, 1000000ULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct omap3_vc_timings {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u32 voltsetup1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u32 voltsetup2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct omap3_vc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct voltagedomain *vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u32 voltctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u32 voltsetup1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u32 voltsetup2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct omap3_vc_timings timings[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static struct omap3_vc vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) void omap3_vc_set_pmic_signaling(int core_next_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct voltagedomain *vd = vc.vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct omap3_vc_timings *c = vc.timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 voltctrl, voltsetup1, voltsetup2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) voltctrl = vc.voltctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) voltsetup1 = vc.voltsetup1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) voltsetup2 = vc.voltsetup2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) switch (core_next_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) case PWRDM_POWER_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) voltctrl &= ~(OMAP3430_PRM_VOLTCTRL_AUTO_RET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) voltctrl |= OMAP3430_PRM_VOLTCTRL_AUTO_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (voltctrl & OMAP3430_PRM_VOLTCTRL_SEL_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) voltsetup2 = c->voltsetup2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) voltsetup1 = c->voltsetup1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) case PWRDM_POWER_RET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) c++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) voltctrl &= ~(OMAP3430_PRM_VOLTCTRL_AUTO_OFF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) voltctrl |= OMAP3430_PRM_VOLTCTRL_AUTO_RET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) voltsetup1 = c->voltsetup1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (voltctrl != vc.voltctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) vd->write(voltctrl, OMAP3_PRM_VOLTCTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) vc.voltctrl = voltctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (voltsetup1 != vc.voltsetup1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) vd->write(c->voltsetup1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) OMAP3_PRM_VOLTSETUP1_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) vc.voltsetup1 = voltsetup1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (voltsetup2 != vc.voltsetup2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) vd->write(c->voltsetup2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) OMAP3_PRM_VOLTSETUP2_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) vc.voltsetup2 = voltsetup2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) void omap4_vc_set_pmic_signaling(int core_next_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct voltagedomain *vd = vc.vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (!vd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) switch (core_next_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) case PWRDM_POWER_RET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) val = OMAP4_VDD_RET_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) val = OMAP4_VDD_DEFAULT_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) vd->write(val, OMAP4_PRM_VOLTCTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * Configure signal polarity for sys_clkreq and sys_off_mode pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * as the default values are wrong and can cause the system to hang
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * if any twl4030 scripts are loaded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static void __init omap3_vc_init_pmic_signaling(struct voltagedomain *voltdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (vc.vd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) vc.vd = voltdm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) val = voltdm->read(OMAP3_PRM_POLCTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (!(val & OMAP3430_PRM_POLCTRL_CLKREQ_POL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) (val & OMAP3430_PRM_POLCTRL_OFFMODE_POL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) val |= OMAP3430_PRM_POLCTRL_CLKREQ_POL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) val &= ~OMAP3430_PRM_POLCTRL_OFFMODE_POL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) pr_debug("PM: fixing sys_clkreq and sys_off_mode polarity to 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) voltdm->write(val, OMAP3_PRM_POLCTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * By default let's use I2C4 signaling for retention idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * and sys_off_mode pin signaling for off idle. This way we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * have sys_clk_req pin go down for retention and both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * sys_clk_req and sys_off_mode pins will go down for off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * idle. And we can also scale voltages to zero for off-idle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * Note that no actual voltage scaling during off-idle will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * happen unless the board specific twl4030 PMIC scripts are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * loaded. See also omap_vc_i2c_init for comments regarding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * erratum i531.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) val = voltdm->read(OMAP3_PRM_VOLTCTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (!(val & OMAP3430_PRM_VOLTCTRL_SEL_OFF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) val |= OMAP3430_PRM_VOLTCTRL_SEL_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) pr_debug("PM: setting voltctrl sys_off_mode signaling to 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) voltdm->write(val, OMAP3_PRM_VOLTCTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) vc.voltctrl = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) omap3_vc_set_pmic_signaling(PWRDM_POWER_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static void omap3_init_voltsetup1(struct voltagedomain *voltdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct omap3_vc_timings *c, u32 idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) val = (voltdm->vc_param->on - idle) / voltdm->pmic->slew_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) val *= voltdm->sys_clk.rate / 8 / 1000000 + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) val <<= __ffs(voltdm->vfsm->voltsetup_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) c->voltsetup1 &= ~voltdm->vfsm->voltsetup_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) c->voltsetup1 |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * omap3_set_i2c_timings - sets i2c sleep timings for a channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * @voltdm: channel to configure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * @off_mode: select whether retention or off mode values used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * Calculates and sets up voltage controller to use I2C based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * voltage scaling for sleep modes. This can be used for either off mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * or retention. Off mode has additionally an option to use sys_off_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * pad, which uses a global signal to program the whole power IC to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * off-mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * Note that pmic is not controlling the voltage scaling during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * retention signaled over I2C4, so we can keep voltsetup2 as 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * And the oscillator is not shut off over I2C4, so no need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * set clksetup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static void omap3_set_i2c_timings(struct voltagedomain *voltdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct omap3_vc_timings *c = vc.timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* Configure PRWDM_POWER_OFF over I2C4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) omap3_init_voltsetup1(voltdm, c, voltdm->vc_param->off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) c++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* Configure PRWDM_POWER_RET over I2C4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) omap3_init_voltsetup1(voltdm, c, voltdm->vc_param->ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * omap3_set_off_timings - sets off-mode timings for a channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * @voltdm: channel to configure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * Calculates and sets up off-mode timings for a channel. Off-mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * can use either I2C based voltage scaling, or alternatively
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * sys_off_mode pad can be used to send a global command to power IC.n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * sys_off_mode has the additional benefit that voltages can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * scaled to zero volt level with TWL4030 / TWL5030, I2C can only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * scale to 600mV.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * Note that omap is not controlling the voltage scaling during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * off idle signaled by sys_off_mode, so we can keep voltsetup1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * as 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static void omap3_set_off_timings(struct voltagedomain *voltdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct omap3_vc_timings *c = vc.timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u32 tstart, tshut, clksetup, voltoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (c->voltsetup2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) omap_pm_get_oscillator(&tstart, &tshut);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (tstart == ULONG_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) pr_debug("PM: oscillator start-up time not initialized, using 10ms\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) clksetup = omap_usec_to_32k(10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) clksetup = omap_usec_to_32k(tstart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * For twl4030 errata 27, we need to allow minimum ~488.32 us wait to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * switch from HFCLKIN to internal oscillator. That means timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * have voltoffset fixed to 0xa in rounded up 32 KiHz cycles. And
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * that means we can calculate the value based on the oscillator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * start-up time since voltoffset2 = clksetup - voltoffset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) voltoffset = omap_usec_to_32k(488);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) c->voltsetup2 = clksetup - voltoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) voltdm->write(clksetup, OMAP3_PRM_CLKSETUP_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) voltdm->write(voltoffset, OMAP3_PRM_VOLTOFFSET_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) omap3_vc_init_pmic_signaling(voltdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) omap3_set_off_timings(voltdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) omap3_set_i2c_timings(voltdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * omap4_calc_volt_ramp - calculates voltage ramping delays on omap4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * @voltdm: channel to calculate values for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * @voltage_diff: voltage difference in microvolts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * Calculates voltage ramp prescaler + counter values for a voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * difference on omap4. Returns a field value suitable for writing to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * VOLTSETUP register for a channel in following format:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * bits[8:9] prescaler ... bits[0:5] counter. See OMAP4 TRM for reference.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static u32 omap4_calc_volt_ramp(struct voltagedomain *voltdm, u32 voltage_diff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) u32 prescaler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) u32 cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u32 time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) time = voltage_diff / voltdm->pmic->slew_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) cycles = voltdm->sys_clk.rate / 1000 * time / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) cycles /= 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) prescaler = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* shift to next prescaler until no overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* scale for div 256 = 64 * 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (cycles > 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) cycles /= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) prescaler++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* scale for div 512 = 256 * 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (cycles > 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) cycles /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) prescaler++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* scale for div 2048 = 512 * 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (cycles > 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) cycles /= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) prescaler++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* check for overflow => invalid ramp time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (cycles > 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) pr_warn("%s: invalid setuptime for vdd_%s\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) voltdm->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) cycles++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return (prescaler << OMAP4430_RAMP_UP_PRESCAL_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) (cycles << OMAP4430_RAMP_UP_COUNT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * omap4_usec_to_val_scrm - convert microsecond value to SCRM module bitfield
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * @usec: microseconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * @shift: number of bits to shift left
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * @mask: bitfield mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * Converts microsecond value to OMAP4 SCRM bitfield. Bitfield is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * shifted to requested position, and checked agains the mask value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * If larger, forced to the max value of the field (i.e. the mask itself.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * Returns the SCRM bitfield value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static u32 omap4_usec_to_val_scrm(u32 usec, int shift, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) val = omap_usec_to_32k(usec) << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* Check for overflow, if yes, force to max value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (val > mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) val = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * omap4_set_timings - set voltage ramp timings for a channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * @voltdm: channel to configure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * @off_mode: whether off-mode values are used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * Calculates and sets the voltage ramp up / down values for a channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static void omap4_set_timings(struct voltagedomain *voltdm, bool off_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) u32 ramp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) u32 tstart, tshut;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (off_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ramp = omap4_calc_volt_ramp(voltdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) voltdm->vc_param->on - voltdm->vc_param->off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) offset = voltdm->vfsm->voltsetup_off_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ramp = omap4_calc_volt_ramp(voltdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) voltdm->vc_param->on - voltdm->vc_param->ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) offset = voltdm->vfsm->voltsetup_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (!ramp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) val = voltdm->read(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) val |= ramp << OMAP4430_RAMP_DOWN_COUNT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) val |= ramp << OMAP4430_RAMP_UP_COUNT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) voltdm->write(val, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) omap_pm_get_oscillator(&tstart, &tshut);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) val = omap4_usec_to_val_scrm(tstart, OMAP4_SETUPTIME_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) OMAP4_SETUPTIME_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) val |= omap4_usec_to_val_scrm(tshut, OMAP4_DOWNTIME_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) OMAP4_DOWNTIME_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) writel_relaxed(val, OMAP4_SCRM_CLKSETUPTIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static void __init omap4_vc_init_pmic_signaling(struct voltagedomain *voltdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (vc.vd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) vc.vd = voltdm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) voltdm->write(OMAP4_VDD_DEFAULT_VAL, OMAP4_PRM_VOLTCTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* OMAP4 specific voltage init functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) omap4_vc_init_pmic_signaling(voltdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) omap4_set_timings(voltdm, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) omap4_set_timings(voltdm, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct i2c_init_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) u8 loadbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) u8 load;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) u8 hsscll_38_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) u8 hsscll_26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) u8 hsscll_19_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) u8 hsscll_16_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) u8 hsscll_12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static const struct i2c_init_data omap4_i2c_timing_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .load = 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .loadbits = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .hsscll_38_4 = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .hsscll_26 = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .hsscll_19_2 = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .hsscll_16_8 = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .hsscll_12 = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .load = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .loadbits = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .hsscll_38_4 = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .hsscll_26 = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .hsscll_19_2 = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .hsscll_16_8 = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .hsscll_12 = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .load = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .loadbits = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .hsscll_38_4 = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .hsscll_26 = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .hsscll_19_2 = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .hsscll_16_8 = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .hsscll_12 = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .load = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .loadbits = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .hsscll_38_4 = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .hsscll_26 = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .hsscll_19_2 = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .hsscll_16_8 = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .hsscll_12 = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * omap4_vc_i2c_timing_init - sets up board I2C timing parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * @voltdm: voltagedomain pointer to get data from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * Use PMIC + board supplied settings for calculating the total I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * channel capacitance and set the timing parameters based on this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * Pre-calculated values are provided in data tables, as it is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * too straightforward to calculate these runtime.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static void __init omap4_vc_i2c_timing_init(struct voltagedomain *voltdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) u32 capacitance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) u16 hsscll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) const struct i2c_init_data *i2c_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (!voltdm->pmic->i2c_high_speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) pr_info("%s: using bootloader low-speed timings\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* PCB trace capacitance, 0.125pF / mm => mm / 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) capacitance = DIV_ROUND_UP(sr_i2c_pcb_length, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* OMAP pad capacitance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) capacitance += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) /* PMIC pad capacitance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) capacitance += voltdm->pmic->i2c_pad_load;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* Search for capacitance match in the table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) i2c_data = omap4_i2c_timing_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) while (i2c_data->load > capacitance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) i2c_data++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* Select proper values based on sysclk frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) switch (voltdm->sys_clk.rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) case 38400000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) hsscll = i2c_data->hsscll_38_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) case 26000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) hsscll = i2c_data->hsscll_26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) case 19200000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) hsscll = i2c_data->hsscll_19_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) case 16800000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) hsscll = i2c_data->hsscll_16_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) case 12000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) hsscll = i2c_data->hsscll_12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) pr_warn("%s: unsupported sysclk rate: %d!\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) voltdm->sys_clk.rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /* Loadbits define pull setup for the I2C channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) val = i2c_data->loadbits << 25 | i2c_data->loadbits << 29;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /* Write to SYSCTRL_PADCONF_WKUP_CTRL_I2C_2 to setup I2C pull */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) writel_relaxed(val, OMAP2_L4_IO_ADDRESS(OMAP4_CTRL_MODULE_PAD_WKUP +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* HSSCLH can always be zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) val = hsscll << OMAP4430_HSSCLL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) val |= (0x28 << OMAP4430_SCLL_SHIFT | 0x2c << OMAP4430_SCLH_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /* Write setup times to I2C config register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) voltdm->write(val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) * omap_vc_i2c_init - initialize I2C interface to PMIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) * @voltdm: voltage domain containing VC data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) * Use PMIC supplied settings for I2C high-speed mode and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * master code (if set) and program the VC I2C configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * The VC I2C configuration is common to all VC channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * so this function only configures I2C for the first VC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * channel registers. All other VC channels will use the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * same configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static void __init omap_vc_i2c_init(struct voltagedomain *voltdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) struct omap_vc_channel *vc = voltdm->vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static bool initialized;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static bool i2c_high_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) u8 mcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (initialized) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (voltdm->pmic->i2c_high_speed != i2c_high_speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) pr_warn("%s: I2C config for vdd_%s does not match other channels (%u).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) __func__, voltdm->name, i2c_high_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) * Note that for omap3 OMAP3430_SREN_MASK clears SREN to work around
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) * erratum i531 "Extra Power Consumed When Repeated Start Operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) * Mode Is Enabled on I2C Interface Dedicated for Smart Reflex (I2C4)".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * Otherwise I2C4 eventually leads into about 23mW extra power being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * consumed even during off idle using VMODE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) i2c_high_speed = voltdm->pmic->i2c_high_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (i2c_high_speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) voltdm->rmw(vc->common->i2c_cfg_clear_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) vc->common->i2c_cfg_hsen_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) vc->common->i2c_cfg_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) mcode = voltdm->pmic->i2c_mcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (mcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) voltdm->rmw(vc->common->i2c_mcode_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) mcode << __ffs(vc->common->i2c_mcode_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) vc->common->i2c_cfg_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (cpu_is_omap44xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) omap4_vc_i2c_timing_init(voltdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) initialized = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * omap_vc_calc_vsel - calculate vsel value for a channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * @voltdm: channel to calculate value for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * @uvolt: microvolt value to convert to vsel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) * Converts a microvolt value to vsel value for the used PMIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) * This checks whether the microvolt value is out of bounds, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * adjusts the value accordingly. If unsupported value detected,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) * warning is thrown.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static u8 omap_vc_calc_vsel(struct voltagedomain *voltdm, u32 uvolt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (voltdm->pmic->vddmin > uvolt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) uvolt = voltdm->pmic->vddmin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (voltdm->pmic->vddmax < uvolt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) WARN(1, "%s: voltage not supported by pmic: %u vs max %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) __func__, uvolt, voltdm->pmic->vddmax);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /* Lets try maximum value anyway */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) uvolt = voltdm->pmic->vddmax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return voltdm->pmic->uv_to_vsel(uvolt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) * omap_pm_setup_sr_i2c_pcb_length - set length of SR I2C traces on PCB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * @mm: length of the PCB trace in millimetres
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * Sets the PCB trace length for the I2C channel. By default uses 63mm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * This is needed for properly calculating the capacitance value for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) * the PCB trace, and for setting the SR I2C channel timing parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) void __init omap_pm_setup_sr_i2c_pcb_length(u32 mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) sr_i2c_pcb_length = mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) void __init omap_vc_init_channel(struct voltagedomain *voltdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) struct omap_vc_channel *vc = voltdm->vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) pr_err("%s: No PMIC info for vdd_%s\n", __func__, voltdm->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (!voltdm->read || !voltdm->write) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) pr_err("%s: No read/write API for accessing vdd_%s regs\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) __func__, voltdm->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) vc->cfg_channel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (vc->flags & OMAP_VC_CHANNEL_CFG_MUTANT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) vc_cfg_bits = &vc_mutant_channel_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) vc_cfg_bits = &vc_default_channel_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) /* get PMIC/board specific settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) vc->i2c_slave_addr = voltdm->pmic->i2c_slave_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) vc->volt_reg_addr = voltdm->pmic->volt_reg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) vc->cmd_reg_addr = voltdm->pmic->cmd_reg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /* Configure the i2c slave address for this VC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) voltdm->rmw(vc->smps_sa_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) vc->i2c_slave_addr << __ffs(vc->smps_sa_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) vc->smps_sa_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) vc->cfg_channel |= vc_cfg_bits->sa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) * Configure the PMIC register addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) voltdm->rmw(vc->smps_volra_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) vc->volt_reg_addr << __ffs(vc->smps_volra_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) vc->smps_volra_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) vc->cfg_channel |= vc_cfg_bits->rav;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (vc->cmd_reg_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) voltdm->rmw(vc->smps_cmdra_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) vc->smps_cmdra_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) vc->cfg_channel |= vc_cfg_bits->rac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (vc->cmd_reg_addr == vc->volt_reg_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) vc->cfg_channel |= vc_cfg_bits->racen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) /* Set up the on, inactive, retention and off voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) on_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) onlp_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->onlp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) ret_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) off_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) val = ((on_vsel << vc->common->cmd_on_shift) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) (onlp_vsel << vc->common->cmd_onlp_shift) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) (ret_vsel << vc->common->cmd_ret_shift) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) (off_vsel << vc->common->cmd_off_shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) voltdm->write(val, vc->cmdval_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) vc->cfg_channel |= vc_cfg_bits->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /* Channel configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) omap_vc_config_channel(voltdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) omap_vc_i2c_init(voltdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (cpu_is_omap34xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) omap3_vc_init_channel(voltdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) else if (cpu_is_omap44xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) omap4_vc_init_channel(voltdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags