Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #include <linux/platform_data/usb-omap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) /* AM35x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) /* USB 2.0 PHY Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #define CONF2_PHY_GPIOMODE	(1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define CONF2_OTGMODE		(3 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define CONF2_NO_OVERRIDE	(0 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define CONF2_FORCE_HOST	(1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define CONF2_FORCE_DEVICE	(2 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CONF2_FORCE_HOST_VBUS_LOW (3 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CONF2_SESENDEN		(1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CONF2_VBDTCTEN		(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CONF2_REFFREQ_24MHZ	(2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CONF2_REFFREQ_26MHZ	(7 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CONF2_REFFREQ_13MHZ	(6 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CONF2_REFFREQ		(0xf << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CONF2_PHYCLKGD		(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CONF2_VBUSSENSE		(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CONF2_PHY_PLLON		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CONF2_RESET		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CONF2_PHYPWRDN		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CONF2_OTGPWRDN		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CONF2_DATPOL		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* TI81XX specific definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define USBCTRL0	0x620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define USBSTAT0	0x624
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* TI816X PHY controls bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TI816X_USBPHY0_NORMAL_MODE	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TI816X_USBPHY_REFCLK_OSC	(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* TI814X PHY controls bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define USBPHY_CM_PWRDN		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define USBPHY_OTG_PWRDN	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define USBPHY_CHGDET_DIS	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define USBPHY_CHGDET_RSTRT	(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define USBPHY_SRCONDM		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define USBPHY_SINKONDP		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define USBPHY_CHGISINK_EN	(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define USBPHY_CHGVSRC_EN	(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define USBPHY_DMPULLUP		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define USBPHY_DPPULLUP		(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define USBPHY_CDET_EXTCTL	(1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define USBPHY_GPIO_MODE	(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define USBPHY_DPOPBUFCTL	(1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define USBPHY_DMOPBUFCTL	(1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define USBPHY_DPINPUT		(1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define USBPHY_DMINPUT		(1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define USBPHY_DPGPIO_PD	(1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define USBPHY_DMGPIO_PD	(1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define USBPHY_OTGVDET_EN	(1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define USBPHY_OTGSESSEND_EN	(1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define USBPHY_DATA_POLARITY	(1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct usbhs_phy_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	int port;		/* 1 indexed port number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	int reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	int vcc_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	bool vcc_polarity;	/* 1 active high, 0 active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) extern void usb_musb_init(struct omap_musb_board_data *board_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) extern void usbhs_init(struct usbhs_omap_platform_data *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) extern int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) extern void am35x_musb_reset(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) extern void am35x_musb_phy_power(u8 on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) extern void am35x_musb_clear_irq(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) extern void am35x_set_mode(u8 musb_mode);