^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * linux/arch/arm/mach-omap2/timer.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * OMAP2 GP timer support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2009 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Update to use new clocksource/clockevent layers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2007 MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Original driver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Copyright (C) 2005 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Author: Paul Mundt <paul.mundt@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Juha Yrjölä <juha.yrjola@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * OMAP Dual-mode timer framework support by Timo Teras
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Some parts based off of TI's 24xx code:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Copyright (C) 2004-2009 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Roughly modelled after the OMAP1 MPU timer code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "control.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "omap-secure.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define REALTIME_COUNTER_BASE 0x48243200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define INCREMENTER_NUMERATOR_OFFSET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define NUMERATOR_DENUMERATOR_MASK 0xfffff000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static unsigned long arch_timer_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) void set_cntfreq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * The realtime counter also called master counter, is a free-running
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * counter, which is related to real time. It produces the count used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * by the CPU local timer peripherals in the MPU cluster. The timer counts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * at a rate of 6.144 MHz. Because the device operates on different clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * in different power modes, the master counter shifts operation between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * clocks, adjusting the increment per clock in hardware accordingly to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * maintain a constant count rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static void __init realtime_counter_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static struct clk *sys_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned long long num, den;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) pr_err("%s: ioremap failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) sys_clk = clk_get(NULL, "sys_clkin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (IS_ERR(sys_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) pr_err("%s: failed to get system clock handle\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) rate = clk_get_rate(sys_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (soc_is_dra7xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * Errata i856 says the 32.768KHz crystal does not start at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * power on, so the CPU falls back to an emulated 32KHz clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * based on sysclk / 610 instead. This causes the master counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * (OR sysclk * 75 / 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * This affects at least the DRA7/AM572x 1.0, 1.1 revisions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * Of course any board built without a populated 32.768KHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * crystal would also need this fix even if the CPU is fixed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * Either case can be detected by using the two speedselect bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * If they are not 0, then the 32.768KHz clock driving the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * coarse counter that corrects the fine counter every time it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * ticks is actually rate/610 rather than 32.768KHz and we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * should compensate to avoid the 570ppm (at 20MHz, much worse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * at other rates) too fast system time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (reg & DRA7_SPEEDSELECT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) num = 75;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) den = 244;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) goto sysclk1_based;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Numerator/denumerator values refer TRM Realtime Counter section */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) case 12000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) num = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) den = 125;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) case 13000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) num = 768;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) den = 1625;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) case 19200000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) num = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) den = 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) case 20000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) num = 192;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) den = 625;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) case 26000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) num = 384;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) den = 1625;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) case 27000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) num = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) den = 1125;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) case 38400000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Program it for 38.4 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) num = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) den = 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) sysclk1_based:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Program numerator and denumerator registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) NUMERATOR_DENUMERATOR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) reg |= num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) reg = readl_relaxed(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) NUMERATOR_DENUMERATOR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) reg |= den;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) set_cntfreq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) void __init omap5_realtime_timer_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) omap_clk_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) realtime_counter_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) timer_probe();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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