^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include "iomap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include "control.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "prm3xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define TI81XX_PRM_DEVICE_RSTCTRL 0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define TI81XX_GLOBAL_RST_COLD BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * ti81xx_restart - trigger a software restart of the SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * @cmd: passed from the userspace program rebooting the system (if provided)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Resets the SoC. For @cmd, see the 'reboot' syscall in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * kernel/sys.c. No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * NOTE: Warm reset does not seem to work, may require resetting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * clocks to bypass mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) void ti81xx_restart(enum reboot_mode mode, const char *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) omap2_prm_set_mod_reg_bits(TI81XX_GLOBAL_RST_COLD, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) TI81XX_PRM_DEVICE_RSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) }