^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mach-omap2/sram243x.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Omap2 specific functions that need to be run in internal SRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * (C) Copyright 2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Texas Instruments, <www.ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Richard Woodruff <r-woodruff2@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Richard Woodruff notes that any changes to this code must be carefully
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * audited and tested to ensure that they don't cause a TLB miss while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * the SDRAM is inaccessible. Such a situation will crash the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * since it will cause the ARM MMU to attempt to walk the page tables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * These crashes may be intermittent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "iomap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "prm2xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "cm2xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "sdrc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .align 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) ENTRY(omap243x_sram_ddr_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) stmfd sp!, {r0 - r12, lr} @ save registers on stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) mov r12, r2 @ capture CS1 vs CS0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) mov r8, r3 @ capture force parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* frequency shift down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) ldr r2, omap243x_sdi_cm_clksel2_pll @ get address of dpllout reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) mov r3, #0x1 @ value for 1x operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) str r3, [r2] @ go to L1-freq operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* voltage shift down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) mov r9, #0x1 @ set up for L1 voltage call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) bl voltage_shift @ go drop voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* dll lock mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) ldr r11, omap243x_sdi_sdrc_dlla_ctrl @ addr of dlla ctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ldr r10, [r11] @ get current val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) cmp r12, #0x1 @ cs1 base (2422 es2.05/1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) addeq r11, r11, #0x8 @ if cs1 base, move to DLLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) mvn r9, #0x4 @ mask to get clear bit2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) and r10, r10, r9 @ clear bit2 for lock mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) orr r10, r10, #0x2 @ 90 degree phase for all below 133MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) str r10, [r11] @ commit to DLLA_CTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) bl i_dll_wait @ wait for dll to lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* get dll value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) add r11, r11, #0x4 @ get addr of status reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ldr r10, [r11] @ get locked value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* voltage shift up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) mov r9, #0x0 @ shift back to L0-voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) bl voltage_shift @ go raise voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* frequency shift up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) mov r3, #0x2 @ value for 2x operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) str r3, [r2] @ go to L0-freq operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* reset entry mode for dllctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) sub r11, r11, #0x4 @ move from status to ctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) cmp r12, #0x1 @ normalize if cs1 based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) subeq r11, r11, #0x8 @ possibly back to DLLA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) cmp r8, #0x1 @ if forced unlock exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) orreq r1, r1, #0x4 @ make sure exit with unlocked value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) str r1, [r11] @ restore DLLA_CTRL high value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) add r11, r11, #0x8 @ move to DLLB_CTRL addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) str r1, [r11] @ set value DLLB_CTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) bl i_dll_wait @ wait for possible lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* set up for return, DDR should be good */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) str r10, [r0] @ write dll_status and return counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ldmfd sp!, {r0 - r12, pc} @ restore regs and return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* ensure the DLL has relocked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) i_dll_wait:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) i_dll_delay:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) subs r4, r4, #0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) bne i_dll_delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * shift up or down voltage, use R9 as input to tell level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * wait for it to finish, use 32k sync counter, 1tick=31uS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) voltage_shift:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ldr r4, omap243x_sdi_prcm_voltctrl @ get addr of volt ctrl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ldr r5, [r4] @ get value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ldr r6, prcm_mask_val @ get value of mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) and r5, r5, r6 @ apply mask to clear bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) str r5, [r4] @ set up for change.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) mov r3, #0x4000 @ get val for force
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) orr r5, r5, r3 @ build value for force
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) str r5, [r4] @ Force transition to L1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ldr r3, omap243x_sdi_timer_32ksynct_cr @ get addr of counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ldr r5, [r3] @ get value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) add r5, r5, #0x3 @ give it at most 93uS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) volt_delay:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ldr r7, [r3] @ get timer value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) cmp r5, r7 @ time up?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) bhi volt_delay @ not yet->branch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ret lr @ back to caller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) omap243x_sdi_cm_clksel2_pll:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) omap243x_sdi_sdrc_dlla_ctrl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) omap243x_sdi_prcm_voltctrl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .word OMAP2430_PRCM_VOLTCTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) prcm_mask_val:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .word 0xFFFF3FFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) omap243x_sdi_timer_32ksynct_cr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .word OMAP2_L4_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ENTRY(omap243x_sram_ddr_init_sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .word . - omap243x_sram_ddr_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * Reprograms memory timings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .align 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ENTRY(omap243x_sram_reprogram_sdrc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) stmfd sp!, {r0 - r10, lr} @ save registers on stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) mov r3, #0x0 @ clear for mrc call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ldr r6, omap243x_srs_sdrc_rfr_ctrl @ get addr of refresh reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) ldr r5, [r6] @ get value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) mov r5, r5, lsr #8 @ isolate rfr field and drop burst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) cmp r0, #0x1 @ going to half speed?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) movne r9, #0x0 @ if up set flag up for pre up, hi volt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) blne voltage_shift_c @ adjust voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) cmp r0, #0x1 @ going to half speed (post branch link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) moveq r5, r5, lsr #1 @ divide by 2 if to half
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) movne r5, r5, lsl #1 @ mult by 2 if to full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) mov r5, r5, lsl #8 @ put rfr field back into place
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) add r5, r5, #0x1 @ turn on burst of 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ldr r4, omap243x_srs_cm_clksel2_pll @ get address of out reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ldr r3, [r4] @ get curr value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) orr r3, r3, #0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) bic r3, r3, #0x3 @ clear lower bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) orr r3, r3, r0 @ new state value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) str r3, [r4] @ set new state (pll/x, x=1 or 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) moveq r9, #0x1 @ if speed down, post down, drop volt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) bleq voltage_shift_c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) mcr p15, 0, r3, c7, c10, 4 @ memory barrier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) str r5, [r6] @ set new RFR_1 value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) add r6, r6, #0x30 @ get RFR_2 addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) str r5, [r6] @ set RFR_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) bne freq_out @ leave if SDR, no DLL function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* With DDR, we need to take care of the DLL for the frequency change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ldr r2, omap243x_srs_sdrc_dlla_ctrl @ addr of dlla ctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) str r1, [r2] @ write out new SDRC_DLLA_CTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) add r2, r2, #0x8 @ addr to SDRC_DLLB_CTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) str r1, [r2] @ commit to SDRC_DLLB_CTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) dll_wait:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) subs r1, r1, #0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) bne dll_wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) freq_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ldmfd sp!, {r0 - r10, pc} @ restore regs and return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * shift up or down voltage, use R9 as input to tell level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * wait for it to finish, use 32k sync counter, 1tick=31uS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) voltage_shift_c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ldr r10, omap243x_srs_prcm_voltctrl @ get addr of volt ctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ldr r8, [r10] @ get value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ldr r7, ddr_prcm_mask_val @ get value of mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) and r8, r8, r7 @ apply mask to clear bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) str r8, [r10] @ set up for change.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) mov r7, #0x4000 @ get val for force
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) orr r8, r8, r7 @ build value for force
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) str r8, [r10] @ Force transition to L1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ldr r10, omap243x_srs_timer_32ksynct @ get addr of counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ldr r8, [r10] @ get value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) add r8, r8, #0x2 @ give it at most 62uS (min 31+)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) volt_delay_c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ldr r7, [r10] @ get timer value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) cmp r8, r7 @ time up?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) bhi volt_delay_c @ not yet->branch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ret lr @ back to caller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) omap243x_srs_cm_clksel2_pll:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) omap243x_srs_sdrc_dlla_ctrl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) omap243x_srs_sdrc_rfr_ctrl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .word OMAP243X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) omap243x_srs_prcm_voltctrl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .word OMAP2430_PRCM_VOLTCTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ddr_prcm_mask_val:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .word 0xFFFF3FFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) omap243x_srs_timer_32ksynct:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .word OMAP2_L4_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ENTRY(omap243x_sram_reprogram_sdrc_sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .word . - omap243x_sram_reprogram_sdrc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .align 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ENTRY(omap243x_sram_set_prcm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) stmfd sp!, {r0-r12, lr} @ regs to stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) adr r4, pbegin @ addr of preload start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) adr r8, pend @ addr of preload end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) mcrr p15, 1, r8, r4, c12 @ preload into icache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) pbegin:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* move into fast relock bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ldr r8, omap243x_ssp_pll_ctl @ get addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ldr r5, [r8] @ get val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) mvn r6, #0x3 @ clear mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) and r5, r5, r6 @ clear field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) orr r7, r5, #0x2 @ fast relock val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) str r7, [r8] @ go to fast relock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ldr r4, omap243x_ssp_pll_stat @ addr of stat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) block:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* wait for bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ldr r8, [r4] @ stat value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) and r8, r8, #0x3 @ mask for stat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) cmp r8, #0x1 @ there yet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) bne block @ loop if not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* set new dpll dividers _after_ in bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ldr r4, omap243x_ssp_pll_div @ get addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) str r0, [r4] @ set dpll ctrl val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ldr r4, omap243x_ssp_set_config @ get addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) mov r8, #1 @ valid cfg msk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) str r8, [r4] @ make dividers take
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) mov r4, #100 @ dead spin a bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) wait_a_bit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) subs r4, r4, #1 @ dec loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) bne wait_a_bit @ delay done?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* check if staying in bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) cmp r2, #0x1 @ stay in bypass?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) beq pend @ jump over dpll relock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* relock DPLL with new vals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ldr r5, omap243x_ssp_pll_stat @ get addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ldr r4, omap243x_ssp_pll_ctl @ get addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) orr r8, r7, #0x3 @ val for lock dpll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) str r8, [r4] @ set val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) mov r0, #1000 @ dead spin a bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) wait_more:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) subs r0, r0, #1 @ dec loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) bne wait_more @ delay done?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) wait_lock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ldr r8, [r5] @ get lock val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) and r8, r8, #3 @ isolate field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) cmp r8, #2 @ locked?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) bne wait_lock @ wait if not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) pend:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* update memory timings & briefly lock dll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ldr r4, omap243x_ssp_sdrc_rfr @ get addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) str r1, [r4] @ update refresh timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ldr r11, omap243x_ssp_dlla_ctrl @ get addr of DLLA ctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ldr r10, [r11] @ get current val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) mvn r9, #0x4 @ mask to get clear bit2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) and r10, r10, r9 @ clear bit2 for lock mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) str r10, [r11] @ commit to DLLA_CTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) add r11, r11, #0x8 @ move to dllb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) str r10, [r11] @ hit DLLB also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) wait_dll_lock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) subs r4, r4, #0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) bne wait_dll_lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ldmfd sp!, {r0-r12, pc} @ restore regs and return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) omap243x_ssp_set_config:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .word OMAP2430_PRCM_CLKCFG_CTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) omap243x_ssp_pll_ctl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) omap243x_ssp_pll_stat:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .word OMAP2430_CM_REGADDR(PLL_MOD, CM_IDLEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) omap243x_ssp_pll_div:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) omap243x_ssp_sdrc_rfr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .word OMAP243X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) omap243x_ssp_dlla_ctrl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ENTRY(omap243x_sram_set_prcm_sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .word . - omap243x_sram_set_prcm
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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