Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Interface for functions that need to be run in internal SRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <plat/sram.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 				u32 base_cs, u32 force_unlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 				      u32 mem_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) extern void omap3_sram_restore_context(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* Do not use these */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) extern unsigned long omap24xx_sram_reprogram_clock_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 						u32 base_cs, u32 force_unlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) extern unsigned long omap242x_sram_ddr_init_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 						int bypass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) extern unsigned long omap242x_sram_set_prcm_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 						u32 mem_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) extern unsigned long omap242x_sram_reprogram_sdrc_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 						u32 base_cs, u32 force_unlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) extern unsigned long omap243x_sram_ddr_init_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 						int bypass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) extern unsigned long omap243x_sram_set_prcm_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 						u32 mem_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) extern unsigned long omap243x_sram_reprogram_sdrc_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) extern void omap_push_sram_idle(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static inline void omap_push_sram_idle(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #endif /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)  * OMAP2+: define the SRAM PA addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)  * Used by the SRAM management code and the idle sleep code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OMAP2_SRAM_PA		0x40200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OMAP3_SRAM_PA           0x40200000