^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * OMAP SRAM detection and management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2005 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Written by Tony Lindgren <tony@atomide.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2009-2012 Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/fncpy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/tlb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "iomap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "prm2xxx_3xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "sdrc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "sram.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SRAM_BOOTLOADER_SZ 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OMAP24XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68005048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OMAP24XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68005050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OMAP24XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68005058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OMAP34XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68012848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define OMAP34XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68012850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OMAP34XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68012858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OMAP34XX_VA_ADDR_MATCH2 OMAP2_L3_IO_ADDRESS(0x68012880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_L3_IO_ADDRESS(0x6C000048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GP_DEVICE 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static unsigned long omap_sram_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static unsigned long omap_sram_skip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static unsigned long omap_sram_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * Depending on the target RAMFS firewall setup, the public usable amount of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * SRAM varies. The default accessible size for all device types is 2k. A GP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * device allows ARM11 but not other initiators for full size. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * functionality seems ok until some nice security API happens.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static int is_sram_locked(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* RAMFW: R/W access to all initiators for all qualifier sets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (cpu_is_omap242x()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) writel_relaxed(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) writel_relaxed(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) writel_relaxed(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (cpu_is_omap34xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) writel_relaxed(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) writel_relaxed(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) writel_relaxed(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) writel_relaxed(0x0, OMAP34XX_VA_ADDR_MATCH2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) writel_relaxed(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return 1; /* assume locked with no PPA or security driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * The amount of SRAM depends on the core type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * Note that we cannot try to test for SRAM here because writes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * to secure SRAM will hang the system. Also the SRAM is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * yet mapped at this point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static void __init omap_detect_sram(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) omap_sram_skip = SRAM_BOOTLOADER_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (is_sram_locked()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (cpu_is_omap34xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) omap_sram_start = OMAP3_SRAM_PUB_PA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) omap_sram_size = 0x7000; /* 28K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) omap_sram_skip += SZ_16K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) omap_sram_size = 0x8000; /* 32K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) omap_sram_start = OMAP2_SRAM_PUB_PA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) omap_sram_size = 0x800; /* 2K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (cpu_is_omap34xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) omap_sram_start = OMAP3_SRAM_PA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) omap_sram_size = 0x10000; /* 64K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) omap_sram_start = OMAP2_SRAM_PA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (cpu_is_omap242x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) omap_sram_size = 0xa0000; /* 640K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) else if (cpu_is_omap243x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) omap_sram_size = 0x10000; /* 64K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void __init omap2_map_sram(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int cached = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (cpu_is_omap34xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * SRAM must be marked as non-cached on OMAP3 since the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * CORE DPLL M2 divider change code (in SRAM) runs with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * SDRAM controller disabled, and if it is marked cached,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * the ARM may attempt to write cache lines back to SDRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * which will cause the system to hang.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) cached = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) omap_map_sram(omap_sram_start, omap_sram_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) omap_sram_skip, cached);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 base_cs, u32 force_unlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 base_cs, u32 force_unlock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) BUG_ON(!_omap2_sram_ddr_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) base_cs, force_unlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 mem_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) BUG_ON(!_omap2_sram_reprogram_sdrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) BUG_ON(!_omap2_set_prcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #ifdef CONFIG_SOC_OMAP2420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int __init omap242x_sram_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) omap242x_sram_ddr_init_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) omap242x_sram_reprogram_sdrc_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) omap242x_sram_set_prcm_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static inline int omap242x_sram_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #ifdef CONFIG_SOC_OMAP2430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int __init omap243x_sram_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) omap243x_sram_ddr_init_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) omap243x_sram_reprogram_sdrc_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) omap243x_sram_set_prcm_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static inline int omap243x_sram_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #ifdef CONFIG_ARCH_OMAP3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) void omap3_sram_restore_context(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) omap_sram_reset();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) omap_push_sram_idle();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static inline int omap34xx_sram_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) omap3_sram_restore_context();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static inline int omap34xx_sram_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #endif /* CONFIG_ARCH_OMAP3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int __init omap_sram_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) omap_detect_sram();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) omap2_map_sram();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (cpu_is_omap242x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) omap242x_sram_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) else if (cpu_is_omap2430())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) omap243x_sram_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) else if (cpu_is_omap34xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) omap34xx_sram_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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