Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * OMAP3/OMAP4 smartreflex device file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Author: Thara Gopinath	<thara@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Based originally on code from smartreflex.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 2010 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Thara Gopinath <thara@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Copyright (C) 2008 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * Kalle Jokiniemi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * Copyright (C) 2007 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * Lesly A M <x0080970@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/power/smartreflex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include "omap_device.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include "voltage.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include "control.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include "pm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) static bool sr_enable_on_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /* Read EFUSE values from control registers for OMAP3430 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 				struct omap_sr_data *sr_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	struct omap_sr_nvalue_table *nvalue_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	int i, j, count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	sr_data->nvalue_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	sr_data->nvalue_table = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	while (volt_data[count].volt_nominal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	nvalue_table = kcalloc(count, sizeof(*nvalue_table), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	if (!nvalue_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	for (i = 0, j = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		 * In OMAP4 the efuse registers are 24 bit aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		 * A readl_relaxed will fail for non-32 bit aligned address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		 * and hence the 8-bit read and shift.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		if (cpu_is_omap44xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 			u16 offset = volt_data[i].sr_efuse_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 			v = omap_ctrl_readb(offset) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 				omap_ctrl_readb(offset + 1) << 8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 				omap_ctrl_readb(offset + 2) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 			v = omap_ctrl_readl(volt_data[i].sr_efuse_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		 * Many OMAP SoCs don't have the eFuse values set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		 * For example, pretty much all OMAP3xxx before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		 * ES3.something.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		 * XXX There needs to be some way for board files or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		 * userspace to add these in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		if (v == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		nvalue_table[j].nvalue = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		nvalue_table[j].efuse_offs = volt_data[i].sr_efuse_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		nvalue_table[j].errminlimit = volt_data[i].sr_errminlimit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		nvalue_table[j].volt_nominal = volt_data[i].volt_nominal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		j++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	sr_data->nvalue_table = nvalue_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	sr_data->nvalue_count = j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) extern struct omap_sr_data omap_sr_pdata[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static int __init sr_init_by_name(const char *name, const char *voltdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	struct omap_sr_data *sr_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	struct omap_volt_data *volt_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	static int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	if (!strncmp(name, "smartreflex_mpu_iva", 20) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	    !strncmp(name, "smartreflex_mpu", 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		sr_data = &omap_sr_pdata[OMAP_SR_MPU];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	else if (!strncmp(name, "smartreflex_core", 17))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		sr_data = &omap_sr_pdata[OMAP_SR_CORE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	else if (!strncmp(name, "smartreflex_iva", 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		sr_data = &omap_sr_pdata[OMAP_SR_IVA];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	if (!sr_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		pr_err("%s: Unknown instance %s\n", __func__, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	sr_data->name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	if (cpu_is_omap343x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		sr_data->ip_type = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		sr_data->ip_type = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	sr_data->senn_mod = 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	sr_data->senp_mod = 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		sr_data->err_weight = OMAP3430_SR_ERRWEIGHT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		sr_data->err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		sr_data->accum_data = OMAP3430_SR_ACCUMDATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		if (!(strcmp(sr_data->name, "smartreflex_mpu"))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			sr_data->senn_avgweight = OMAP3430_SR1_SENNAVGWEIGHT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			sr_data->senp_avgweight = OMAP3430_SR1_SENPAVGWEIGHT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			sr_data->senn_avgweight = OMAP3430_SR2_SENNAVGWEIGHT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 			sr_data->senp_avgweight = OMAP3430_SR2_SENPAVGWEIGHT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	sr_data->voltdm = voltdm_lookup(voltdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	if (!sr_data->voltdm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		pr_err("%s: Unable to get voltage domain pointer for VDD %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			__func__, voltdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	omap_voltage_get_volttable(sr_data->voltdm, &volt_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	if (!volt_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		pr_err("%s: No Voltage table registered for VDD%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		       __func__, i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	sr_set_nvalues(volt_data, sr_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	sr_data->enable_on_init = sr_enable_on_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	struct omap_smartreflex_dev_attr *sr_dev_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	sr_dev_attr = (struct omap_smartreflex_dev_attr *)oh->dev_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	if (!sr_dev_attr || !sr_dev_attr->sensor_voltdm_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		pr_err("%s: No voltage domain specified for %s. Cannot initialize\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		       __func__, oh->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	return sr_init_by_name(oh->name, sr_dev_attr->sensor_voltdm_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)  * API to be called from board files to enable smartreflex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)  * autocompensation at init.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) void __init omap_enable_smartreflex_on_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	sr_enable_on_init = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static const char * const omap4_sr_instances[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	"mpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	"iva",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	"core",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const char * const dra7_sr_instances[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	"mpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	"core",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int __init omap_devinit_smartreflex(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	const char * const *sr_inst = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	int i, nr_sr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	if (soc_is_omap44xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		sr_inst = omap4_sr_instances;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		nr_sr = ARRAY_SIZE(omap4_sr_instances);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	} else if (soc_is_dra7xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		sr_inst = dra7_sr_instances;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		nr_sr = ARRAY_SIZE(dra7_sr_instances);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	if (nr_sr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		const char *name, *voltdm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		for (i = 0; i < nr_sr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 			name = kasprintf(GFP_KERNEL, "smartreflex_%s", sr_inst[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			voltdm = sr_inst[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			sr_init_by_name(name, voltdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	return omap_hwmod_for_each_by_class("smartreflex", sr_dev_init, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }