^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP44xx sleep code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2011 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Santosh Shilimkar <santosh.shilimkar@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/smp_scu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/memory.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/hardware/cache-l2x0.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "omap-secure.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "omap44xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "omap4-sar-layout.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) .arch armv7-a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #if defined(CONFIG_SMP) && defined(CONFIG_PM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .arch_extension sec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .macro DO_SMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) dsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) smc #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) dsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #ifdef CONFIG_ARCH_OMAP4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * =============================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * == CPU suspend finisher ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * =============================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * void omap4_finish_suspend(unsigned long cpu_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * This function code saves the CPU context and performs the CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * power down sequence. Calling WFI effectively changes the CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * power domains states to the desired target power state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * @cpu_state : contains context save state (r0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * 0 - No context lost
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * 1 - CPUx L1 and logic lost: MPUSS CSWR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * 2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * 3 - CPUx L1 and logic lost + GIC + L2 lost: MPUSS OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @return: This function never returns for CPU OFF and DORMANT power states.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * Post WFI, CPU transitions to DORMANT or OFF power state and on wake-up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * from this follows a full CPU reset path via ROM code to CPU restore code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * The restore function pointer is stored at CPUx_WAKEUP_NS_PA_ADDR_OFFSET.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * It returns to the caller for CPU INACTIVE and ON power states or in case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * CPU failed to transition to targeted OFF/DORMANT state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * omap4_finish_suspend() calls v7_flush_dcache_all() which doesn't save
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * stack frame and it expects the caller to take care of it. Hence the entire
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * stack frame is saved to avoid possible stack corruption.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ENTRY(omap4_finish_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) stmfd sp!, {r4-r12, lr}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) cmp r0, #0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) beq do_WFI @ No lowpower state, jump to WFI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * Flush all data from the L1 data cache before disabling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * SCTLR.C bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) bl omap4_get_sar_ram_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ldr r9, [r0, #OMAP_TYPE_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) cmp r9, #0x1 @ Check for HS device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) bne skip_secure_l1_clean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) mov r0, #SCU_PM_NORMAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) mov r1, #0xFF @ clean seucre L1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) stmfd r13!, {r4-r12, r14}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ldr r12, =OMAP4_MON_SCU_PWR_INDEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) DO_SMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ldmfd r13!, {r4-r12, r14}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) skip_secure_l1_clean:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) bl v7_flush_dcache_all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * Clear the SCTLR.C bit to prevent further data cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * allocation. Clearing SCTLR.C would make all the data accesses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * strongly ordered and would not hit the cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) mrc p15, 0, r0, c1, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) bic r0, r0, #(1 << 2) @ Disable the C bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) mcr p15, 0, r0, c1, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) bl v7_invalidate_l1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * Switch the CPU from Symmetric Multiprocessing (SMP) mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * to AsymmetricMultiprocessing (AMP) mode by programming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * the SCU power status to DORMANT or OFF mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * This enables the CPU to be taken out of coherency by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * preventing the CPU from receiving cache, TLB, or BTB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * maintenance operations broadcast by other CPUs in the cluster.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) bl omap4_get_sar_ram_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) mov r8, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ldr r9, [r8, #OMAP_TYPE_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) cmp r9, #0x1 @ Check for HS device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) bne scu_gp_set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ands r0, r0, #0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ldreq r0, [r8, #SCU_OFFSET0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ldrne r0, [r8, #SCU_OFFSET1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) mov r1, #0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) stmfd r13!, {r4-r12, r14}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ldr r12, =OMAP4_MON_SCU_PWR_INDEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) DO_SMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ldmfd r13!, {r4-r12, r14}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) b skip_scu_gp_set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) scu_gp_set:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ands r0, r0, #0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ldreq r1, [r8, #SCU_OFFSET0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ldrne r1, [r8, #SCU_OFFSET1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) bl omap4_get_scu_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) bl scu_power_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) skip_scu_gp_set:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) mrc p15, 0, r0, c1, c1, 2 @ Read NSACR data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) tst r0, #(1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) mrcne p15, 0, r0, c1, c0, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) bicne r0, r0, #(1 << 6) @ Disable SMP bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) mcrne p15, 0, r0, c1, c0, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) dsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #ifdef CONFIG_CACHE_L2X0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * Clean and invalidate the L2 cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * Common cache-l2x0.c functions can't be used here since it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * uses spinlocks. We are out of coherency here with data cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * disabled. The spinlock implementation uses exclusive load/store
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * instruction which can fail without data cache being enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * OMAP4 hardware doesn't support exclusive monitor which can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * overcome exclusive access issue. Because of this, CPU can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * lead to deadlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) bl omap4_get_sar_ram_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) mov r8, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) mrc p15, 0, r5, c0, c0, 5 @ Read MPIDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ands r5, r5, #0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ldreq r0, [r8, #L2X0_SAVE_OFFSET0] @ Retrieve L2 state from SAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ldrne r0, [r8, #L2X0_SAVE_OFFSET1] @ memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) cmp r0, #3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) bne do_WFI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #ifdef CONFIG_PL310_ERRATA_727915
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) mov r0, #0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) mov r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) DO_SMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) bl omap4_get_l2cache_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) mov r2, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ldr r0, =0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) str r0, [r2, #L2X0_CLEAN_INV_WAY]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) wait:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ldr r0, [r2, #L2X0_CLEAN_INV_WAY]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ldr r1, =0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ands r0, r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) bne wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #ifdef CONFIG_PL310_ERRATA_727915
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) mov r0, #0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) mov r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) DO_SMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) l2x_sync:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) bl omap4_get_l2cache_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) mov r2, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) mov r0, #0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) str r0, [r2, #L2X0_CACHE_SYNC]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) sync:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ldr r0, [r2, #L2X0_CACHE_SYNC]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ands r0, r0, #0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) bne sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) do_WFI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) bl omap_do_wfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * CPU is here when it failed to enter OFF/DORMANT or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * no low power state was attempted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) mrc p15, 0, r0, c1, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) tst r0, #(1 << 2) @ Check C bit enabled?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) orreq r0, r0, #(1 << 2) @ Enable the C bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) mcreq p15, 0, r0, c1, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * Ensure the CPU power state is set to NORMAL in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * SCU power state so that CPU is back in coherency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * In non-coherent mode CPU can lock-up and lead to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * system deadlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) mrc p15, 0, r0, c1, c0, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) tst r0, #(1 << 6) @ Check SMP bit enabled?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) orreq r0, r0, #(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) mcreq p15, 0, r0, c1, c0, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) bl omap4_get_sar_ram_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) mov r8, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ldr r9, [r8, #OMAP_TYPE_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) cmp r9, #0x1 @ Check for HS device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) bne scu_gp_clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) mov r0, #SCU_PM_NORMAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) mov r1, #0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) stmfd r13!, {r4-r12, r14}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ldr r12, =OMAP4_MON_SCU_PWR_INDEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) DO_SMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ldmfd r13!, {r4-r12, r14}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) b skip_scu_gp_clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) scu_gp_clear:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) bl omap4_get_scu_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) mov r1, #SCU_PM_NORMAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) bl scu_power_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) skip_scu_gp_clear:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) dsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ldmfd sp!, {r4-r12, pc}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ENDPROC(omap4_finish_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * ============================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * == CPU resume entry point ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * ============================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * void omap4_cpu_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * ROM code jumps to this function while waking up from CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * OFF or DORMANT state. Physical address of the function is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * stored in the SAR RAM while entering to OFF or DORMANT mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * The restore function pointer is stored at CPUx_WAKEUP_NS_PA_ADDR_OFFSET.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ENTRY(omap4_cpu_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * init and for CPU1, a secure PPA API provided. CPU0 must be ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * OMAP443X GP devices- SMP bit isn't accessible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * OMAP446X GP devices - SMP bit access is enabled on both CPUs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ldr r8, =OMAP44XX_SAR_RAM_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ldr r9, [r8, #OMAP_TYPE_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) cmp r9, #0x1 @ Skip if GP device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) bne skip_ns_smp_enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) mrc p15, 0, r0, c0, c0, 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ands r0, r0, #0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) beq skip_ns_smp_enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ppa_actrl_retry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) mov r0, #OMAP4_PPA_CPU_ACTRL_SMP_INDEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) adr r1, ppa_zero_params_offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ldr r3, [r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) add r3, r3, r1 @ Pointer to ppa_zero_params
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) mov r1, #0x0 @ Process ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) mov r2, #0x4 @ Flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) mov r6, #0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) mov r12, #0x00 @ Secure Service ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) DO_SMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) cmp r0, #0x0 @ API returns 0 on success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) beq enable_smp_bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) b ppa_actrl_retry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) enable_smp_bit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) mrc p15, 0, r0, c1, c0, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) tst r0, #(1 << 6) @ Check SMP bit enabled?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) orreq r0, r0, #(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) mcreq p15, 0, r0, c1, c0, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) skip_ns_smp_enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #ifdef CONFIG_CACHE_L2X0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * Restore the L2 AUXCTRL and enable the L2 cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * OMAP4_MON_L2X0_AUXCTRL_INDEX = Program the L2X0 AUXCTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * OMAP4_MON_L2X0_CTRL_INDEX = Enable the L2 using L2X0 CTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * register r0 contains value to be programmed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * L2 cache is already invalidate by ROM code as part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * of MPUSS OFF wakeup path.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ldr r2, =OMAP44XX_L2CACHE_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) ldr r0, [r2, #L2X0_CTRL]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) and r0, #0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) cmp r0, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) beq skip_l2en @ Skip if already enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ldr r3, =OMAP44XX_SAR_RAM_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ldr r1, [r3, #OMAP_TYPE_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) cmp r1, #0x1 @ Check for HS device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) bne set_gp_por
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ldr r0, =OMAP4_PPA_L2_POR_INDEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ldr r1, =OMAP44XX_SAR_RAM_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ldr r4, [r1, #L2X0_PREFETCH_CTRL_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) adr r1, ppa_por_params_offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ldr r3, [r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) add r3, r3, r1 @ Pointer to ppa_por_params
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) str r4, [r3, #0x04]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) mov r1, #0x0 @ Process ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) mov r2, #0x4 @ Flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) mov r6, #0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) mov r12, #0x00 @ Secure Service ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) DO_SMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) b set_aux_ctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) set_gp_por:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ldr r1, =OMAP44XX_SAR_RAM_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ldr r0, [r1, #L2X0_PREFETCH_CTRL_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) ldr r12, =OMAP4_MON_L2X0_PREFETCH_INDEX @ Setup L2 PREFETCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) DO_SMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) set_aux_ctrl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ldr r1, =OMAP44XX_SAR_RAM_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ldr r0, [r1, #L2X0_AUXCTRL_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ldr r12, =OMAP4_MON_L2X0_AUXCTRL_INDEX @ Setup L2 AUXCTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) DO_SMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) mov r0, #0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ldr r12, =OMAP4_MON_L2X0_CTRL_INDEX @ Enable L2 cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) DO_SMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) skip_l2en:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) b cpu_resume @ Jump to generic resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ppa_por_params_offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .long ppa_por_params - .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ENDPROC(omap4_cpu_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #endif /* CONFIG_ARCH_OMAP4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #endif /* defined(CONFIG_SMP) && defined(CONFIG_PM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ENTRY(omap_do_wfi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) stmfd sp!, {lr}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #ifdef CONFIG_OMAP_INTERCONNECT_BARRIER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Drain interconnect write buffers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) bl omap_interconnect_sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * Execute an ISB instruction to ensure that all of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * CP15 register changes have been committed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * Execute a barrier instruction to ensure that all cache,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * TLB and branch predictor maintenance operations issued
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * by any CPU in the cluster have completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) dsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) dmb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * Execute a WFI instruction and wait until the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * STANDBYWFI output is asserted to indicate that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * CPU is in idle and low power state. CPU can specualatively
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * prefetch the instructions so add NOPs after WFI. Sixteen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * NOPs as per Cortex-A9 pipeline.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) wfi @ Wait For Interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ldmfd sp!, {pc}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) ppa_zero_params_offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .long ppa_zero_params - .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ENDPROC(omap_do_wfi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .align 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ppa_zero_params:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .word 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ppa_por_params:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .word 1, 0
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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