Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Low level suspend code for AM43XX SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2013-2018 Texas Instruments Incorporated - https://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *	Dave Gerlach, Vaibhav Bedia
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/ti-emif-sram.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/platform_data/pm33xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <asm/hardware/cache-l2x0.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <asm/memory.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "cm33xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "iomap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "omap-secure.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "omap44xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include "pm-asm-offsets.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include "prm33xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include "prcm43xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /* replicated define because linux/bitops.h cannot be included in assembly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define BIT(nr)			(1 << (nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define AM33XX_CM_CLKCTRL_MODULESTATE_DISABLED		0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE		0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE		0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define AM43XX_EMIF_POWEROFF_ENABLE			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define AM43XX_EMIF_POWEROFF_DISABLE			0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define AM43XX_CM_CLKSTCTRL_CLKTRCTRL_SW_SLEEP		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define AM43XX_CM_CLKSTCTRL_CLKTRCTRL_HW_AUTO		0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define AM43XX_CM_BASE					0x44DF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define AM43XX_CM_REGADDR(inst, reg)                           \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)        AM33XX_L4_WK_IO_ADDRESS(AM43XX_CM_BASE + (inst) + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define AM43XX_CM_MPU_CLKSTCTRL AM43XX_CM_REGADDR(AM43XX_CM_MPU_INST, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 					AM43XX_CM_MPU_MPU_CDOFFS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define AM43XX_CM_MPU_MPU_CLKCTRL AM43XX_CM_REGADDR(AM43XX_CM_MPU_INST, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 					AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define AM43XX_CM_PER_EMIF_CLKCTRL  AM43XX_CM_REGADDR(AM43XX_CM_PER_INST, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 					AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define AM43XX_PRM_EMIF_CTRL_OFFSET			0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define RTC_SECONDS_REG					0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define RTC_PMIC_REG					0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define RTC_PMIC_POWER_EN				BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define RTC_PMIC_EXT_WAKEUP_STS				BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define RTC_PMIC_EXT_WAKEUP_POL				BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define RTC_PMIC_EXT_WAKEUP_EN				BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	.arm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	.arch armv7-a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	.arch_extension sec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	.align 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) ENTRY(am43xx_do_wfi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	stmfd	sp!, {r4 - r11, lr}	@ save registers on stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	/* Save wfi_flags arg to data space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	mov	r4, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	adr	r3, am43xx_pm_ro_sram_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	ldr	r2, [r3, #AMX3_PM_RO_SRAM_DATA_VIRT_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	str	r4, [r2, #AMX3_PM_WFI_FLAGS_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #ifdef CONFIG_CACHE_L2X0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	/* Retrieve l2 cache virt address BEFORE we shut off EMIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	ldr	r1, get_l2cache_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	blx	r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	mov	r8, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	/* Only flush cache is we know we are losing MPU context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	tst	r4, #WFI_FLAG_FLUSH_CACHE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	beq	cache_skip_flush
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	 * Flush all data from the L1 and L2 data cache before disabling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	 * SCTLR.C bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	ldr	r1, kernel_flush
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	blx	r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	 * Clear the SCTLR.C bit to prevent further data cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	 * allocation. Clearing SCTLR.C would make all the data accesses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	 * strongly ordered and would not hit the cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	mrc	p15, 0, r0, c1, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	bic	r0, r0, #(1 << 2)	@ Disable the C bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	mcr	p15, 0, r0, c1, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	dsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	 * Invalidate L1 and L2 data cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	ldr	r1, kernel_flush
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	blx	r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #ifdef CONFIG_CACHE_L2X0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	 * Clean and invalidate the L2 cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #ifdef CONFIG_PL310_ERRATA_727915
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	mov	r0, #0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	mov	r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	dsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	smc	#0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	dsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	mov	r0, r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	adr	r4, am43xx_pm_ro_sram_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	ldr	r3, [r4, #AMX3_PM_RO_SRAM_DATA_VIRT_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	mov	r2, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	ldr	r0, [r2, #L2X0_AUX_CTRL]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	str	r0, [r3, #AMX3_PM_L2_AUX_CTRL_VAL_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	ldr	r0, [r2, #L310_PREFETCH_CTRL]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	str	r0, [r3, #AMX3_PM_L2_PREFETCH_CTRL_VAL_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	ldr	r0, l2_val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	str	r0, [r2, #L2X0_CLEAN_INV_WAY]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) wait:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	ldr	r0, [r2, #L2X0_CLEAN_INV_WAY]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	ldr	r1, l2_val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	ands	r0, r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	bne	wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #ifdef CONFIG_PL310_ERRATA_727915
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	mov	r0, #0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	mov	r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	dsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	smc	#0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	dsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) l2x_sync:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	mov	r0, r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	mov	r2, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	mov	r0, #0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	str	r0, [r2, #L2X0_CACHE_SYNC]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) sync:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	ldr	r0, [r2, #L2X0_CACHE_SYNC]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	ands	r0, r0, #0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	bne	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	/* Restore wfi_flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	adr	r3, am43xx_pm_ro_sram_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	ldr	r2, [r3, #AMX3_PM_RO_SRAM_DATA_VIRT_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	ldr	r4, [r2, #AMX3_PM_WFI_FLAGS_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) cache_skip_flush:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	 * If we are trying to enter RTC+DDR mode we must perform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	 * a read from the rtc address space to ensure translation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	 * presence in the TLB to avoid page table walk after DDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	 * is unavailable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	tst	r4, #WFI_FLAG_RTC_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	beq	skip_rtc_va_refresh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	adr	r3, am43xx_pm_ro_sram_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	ldr	r1, [r3, #AMX3_PM_RTC_BASE_VIRT_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	ldr	r0, [r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) skip_rtc_va_refresh:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	/* Check if we want self refresh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	tst	r4, #WFI_FLAG_SELF_REFRESH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	beq	emif_skip_enter_sr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	adr     r9, am43xx_emif_sram_table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	ldr     r3, [r9, #EMIF_PM_ENTER_SR_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	blx     r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) emif_skip_enter_sr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	/* Only necessary if PER is losing context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	tst	r4, #WFI_FLAG_SAVE_EMIF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	beq	emif_skip_save
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	ldr     r3, [r9, #EMIF_PM_SAVE_CONTEXT_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	blx	r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) emif_skip_save:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	/* Only can disable EMIF if we have entered self refresh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	tst	r4, #WFI_FLAG_SELF_REFRESH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	beq	emif_skip_disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	/* Disable EMIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	ldr	r1, am43xx_virt_emif_clkctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	ldr	r2, [r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	bic	r2, r2, #AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	str	r2, [r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) wait_emif_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	ldr	r2, [r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	mov	r3, #AM33XX_CM_CLKCTRL_MODULESTATE_DISABLED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	cmp	r2, r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	bne	wait_emif_disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) emif_skip_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	tst	r4, #WFI_FLAG_RTC_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	beq	skip_rtc_only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	adr	r3, am43xx_pm_ro_sram_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	ldr	r1, [r3, #AMX3_PM_RTC_BASE_VIRT_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	ldr	r0, [r1, #RTC_PMIC_REG]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	orr	r0, r0, #RTC_PMIC_POWER_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	orr	r0, r0, #RTC_PMIC_EXT_WAKEUP_STS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	orr	r0, r0, #RTC_PMIC_EXT_WAKEUP_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	orr	r0, r0, #RTC_PMIC_EXT_WAKEUP_POL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	str	r0, [r1, #RTC_PMIC_REG]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	ldr	r0, [r1, #RTC_PMIC_REG]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	/* Wait for 2 seconds to lose power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	mov	r3, #2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	ldr	r2, [r1, #RTC_SECONDS_REG]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) rtc_loop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	ldr	r0, [r1, #RTC_SECONDS_REG]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	cmp	r0, r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	beq	rtc_loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	mov	r2, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	subs	r3, r3, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	bne	rtc_loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	b	re_enable_emif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) skip_rtc_only:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	tst	r4, #WFI_FLAG_WAKE_M3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	beq	wkup_m3_skip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	 * For the MPU WFI to be registered as an interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	 * to WKUP_M3, MPU_CLKCTRL.MODULEMODE needs to be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	 * to DISABLED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	ldr	r1, am43xx_virt_mpu_clkctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	ldr	r2, [r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	bic	r2, r2, #AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	str	r2, [r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	 * Put MPU CLKDM to SW_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	ldr	r1, am43xx_virt_mpu_clkstctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	mov	r2, #AM43XX_CM_CLKSTCTRL_CLKTRCTRL_SW_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	str	r2, [r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) wkup_m3_skip:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	 * Execute a barrier instruction to ensure that all cache,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	 * TLB and branch predictor maintenance operations issued
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	 * have completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	dsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	dmb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	 * Execute a WFI instruction and wait until the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	 * STANDBYWFI output is asserted to indicate that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	 * CPU is in idle and low power state. CPU can specualatively
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	 * prefetch the instructions so add NOPs after WFI. Sixteen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	 * NOPs as per Cortex-A9 pipeline.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	wfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	/* We come here in case of an abort due to a late interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	ldr	r1, am43xx_virt_mpu_clkstctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	mov	r2, #AM43XX_CM_CLKSTCTRL_CLKTRCTRL_HW_AUTO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	str	r2, [r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	/* Set MPU_CLKCTRL.MODULEMODE back to ENABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	ldr	r1, am43xx_virt_mpu_clkctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	mov	r2, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	str	r2, [r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) re_enable_emif:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	/* Re-enable EMIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	ldr	r1, am43xx_virt_emif_clkctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	mov	r2, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	str	r2, [r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) wait_emif_enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	ldr	r3, [r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	cmp	r2, r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	bne	wait_emif_enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	tst	r4, #WFI_FLAG_FLUSH_CACHE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	beq	cache_skip_restore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	 * Set SCTLR.C bit to allow data cache allocation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	mrc	p15, 0, r0, c1, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	orr	r0, r0, #(1 << 2)	@ Enable the C bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	mcr	p15, 0, r0, c1, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) cache_skip_restore:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	/* Only necessary if PER is losing context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	tst	r4, #WFI_FLAG_SELF_REFRESH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	beq	emif_skip_exit_sr_abt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	adr	r9, am43xx_emif_sram_table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	ldr	r1, [r9, #EMIF_PM_ABORT_SR_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	blx	r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) emif_skip_exit_sr_abt:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	/* Let the suspend code know about the abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	mov	r0, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	ldmfd	sp!, {r4 - r11, pc}	@ restore regs and return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ENDPROC(am43xx_do_wfi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	.align
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ENTRY(am43xx_resume_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	.word . - am43xx_do_wfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ENTRY(am43xx_resume_from_deep_sleep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	/* Set MPU CLKSTCTRL to HW AUTO so that CPUidle works properly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	ldr	r1, am43xx_virt_mpu_clkstctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	mov	r2, #AM43XX_CM_CLKSTCTRL_CLKTRCTRL_HW_AUTO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	str	r2, [r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	/* For AM43xx, use EMIF power down until context is restored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	ldr	r2, am43xx_phys_emif_poweroff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	mov	r1, #AM43XX_EMIF_POWEROFF_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	str	r1, [r2, #0x0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	/* Re-enable EMIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	ldr	r1, am43xx_phys_emif_clkctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	mov	r2, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	str	r2, [r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) wait_emif_enable1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	ldr	r3, [r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	cmp	r2, r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	bne	wait_emif_enable1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	adr     r9, am43xx_emif_sram_table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	ldr     r1, [r9, #EMIF_PM_RESTORE_CONTEXT_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	blx     r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	ldr     r1, [r9, #EMIF_PM_EXIT_SR_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	blx     r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	ldr     r2, am43xx_phys_emif_poweroff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	mov     r1, #AM43XX_EMIF_POWEROFF_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	str     r1, [r2, #0x0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	ldr     r1, [r9, #EMIF_PM_RUN_HW_LEVELING]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	blx     r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #ifdef CONFIG_CACHE_L2X0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	ldr	r2, l2_cache_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	ldr	r0, [r2, #L2X0_CTRL]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	and	r0, #0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	cmp	r0, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	beq	skip_l2en			@ Skip if already enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	adr	r4, am43xx_pm_ro_sram_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	ldr	r3, [r4, #AMX3_PM_RO_SRAM_DATA_PHYS_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	ldr     r0, [r3, #AMX3_PM_L2_PREFETCH_CTRL_VAL_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	ldr	r12, l2_smc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	dsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	smc	#0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	dsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) set_aux_ctrl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	ldr     r0, [r3, #AMX3_PM_L2_AUX_CTRL_VAL_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	ldr	r12, l2_smc2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	dsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	smc	#0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	dsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	/* L2 invalidate on resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	ldr	r0, l2_val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	ldr	r2, l2_cache_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	str	r0, [r2, #L2X0_INV_WAY]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) wait2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	ldr	r0, [r2, #L2X0_INV_WAY]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	ldr	r1, l2_val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	ands	r0, r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	bne	wait2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #ifdef CONFIG_PL310_ERRATA_727915
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	mov	r0, #0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	mov	r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	dsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	smc	#0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	dsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) l2x_sync2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	ldr	r2, l2_cache_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	mov	r0, #0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	str	r0, [r2, #L2X0_CACHE_SYNC]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) sync2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	ldr	r0, [r2, #L2X0_CACHE_SYNC]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	ands	r0, r0, #0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	bne	sync2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	mov	r0, #0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	ldr	r12, l2_smc3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	dsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	smc	#0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	dsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) skip_l2en:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	/* We are back. Branch to the common CPU resume routine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	mov	r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	ldr	pc, resume_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ENDPROC(am43xx_resume_from_deep_sleep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)  * Local variables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	.align
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) kernel_flush:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	.word   v7_flush_dcache_all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ddr_start:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	.word	PAGE_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) am43xx_phys_emif_poweroff:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	.word   (AM43XX_CM_BASE + AM43XX_PRM_DEVICE_INST + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 		 AM43XX_PRM_EMIF_CTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) am43xx_virt_mpu_clkstctrl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	.word	(AM43XX_CM_MPU_CLKSTCTRL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) am43xx_virt_mpu_clkctrl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	.word	(AM43XX_CM_MPU_MPU_CLKCTRL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) am43xx_virt_emif_clkctrl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	.word	(AM43XX_CM_PER_EMIF_CLKCTRL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) am43xx_phys_emif_clkctrl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	.word	(AM43XX_CM_BASE + AM43XX_CM_PER_INST + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 		 AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #ifdef CONFIG_CACHE_L2X0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* L2 cache related defines for AM437x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) get_l2cache_base:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	.word	omap4_get_l2cache_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) l2_cache_base:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	.word	OMAP44XX_L2CACHE_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) l2_smc1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	.word	OMAP4_MON_L2X0_PREFETCH_INDEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) l2_smc2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	.word	OMAP4_MON_L2X0_AUXCTRL_INDEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) l2_smc3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	.word	OMAP4_MON_L2X0_CTRL_INDEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) l2_val:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	.word	0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .align 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* DDR related defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ENTRY(am43xx_emif_sram_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	.space EMIF_PM_FUNCTIONS_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ENTRY(am43xx_pm_sram)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	.word am43xx_do_wfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	.word am43xx_do_wfi_sz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	.word am43xx_resume_offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	.word am43xx_emif_sram_table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	.word am43xx_pm_ro_sram_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) resume_addr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	.word   cpu_resume - PAGE_OFFSET + 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .align 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) ENTRY(am43xx_pm_ro_sram_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	.space AMX3_PM_RO_SRAM_DATA_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ENTRY(am43xx_do_wfi_sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	.word	. - am43xx_do_wfi