Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Low level suspend code for AM33XX SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2012-2018 Texas Instruments Incorporated - https://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *	Dave Gerlach, Vaibhav Bedia
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/platform_data/pm33xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/ti-emif-sram.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <asm/memory.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "iomap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "cm33xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "pm-asm-offsets.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define AM33XX_CM_CLKCTRL_MODULESTATE_DISABLED			0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE			0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE			0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /* replicated define because linux/bitops.h cannot be included in assembly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define BIT(nr)			(1 << (nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	.arm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	.arch armv7-a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	.align 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) ENTRY(am33xx_do_wfi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	stmfd	sp!, {r4 - r11, lr}	@ save registers on stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	/* Save wfi_flags arg to data space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	mov	r4, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	adr	r3, am33xx_pm_ro_sram_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	ldr	r2, [r3, #AMX3_PM_RO_SRAM_DATA_VIRT_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	str	r4, [r2, #AMX3_PM_WFI_FLAGS_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	/* Only flush cache is we know we are losing MPU context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	tst	r4, #WFI_FLAG_FLUSH_CACHE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	beq	cache_skip_flush
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	 * Flush all data from the L1 and L2 data cache before disabling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	 * SCTLR.C bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	ldr	r1, kernel_flush
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	blx	r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	 * Clear the SCTLR.C bit to prevent further data cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	 * allocation. Clearing SCTLR.C would make all the data accesses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	 * strongly ordered and would not hit the cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	mrc	p15, 0, r0, c1, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	bic	r0, r0, #(1 << 2)	@ Disable the C bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	mcr	p15, 0, r0, c1, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	 * Invalidate L1 and L2 data cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	ldr	r1, kernel_flush
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	blx	r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	adr	r3, am33xx_pm_ro_sram_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	ldr	r2, [r3, #AMX3_PM_RO_SRAM_DATA_VIRT_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	ldr	r4, [r2, #AMX3_PM_WFI_FLAGS_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) cache_skip_flush:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	/* Check if we want self refresh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	tst	r4, #WFI_FLAG_SELF_REFRESH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	beq	emif_skip_enter_sr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	adr	r9, am33xx_emif_sram_table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	ldr	r3, [r9, #EMIF_PM_ENTER_SR_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	blx	r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) emif_skip_enter_sr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	/* Only necessary if PER is losing context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	tst	r4, #WFI_FLAG_SAVE_EMIF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	beq	emif_skip_save
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	ldr	r3, [r9, #EMIF_PM_SAVE_CONTEXT_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	blx	r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) emif_skip_save:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	/* Only can disable EMIF if we have entered self refresh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	tst     r4, #WFI_FLAG_SELF_REFRESH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	beq     emif_skip_disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	/* Disable EMIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	ldr     r1, virt_emif_clkctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	ldr     r2, [r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	bic     r2, r2, #AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	str     r2, [r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	ldr	r1, virt_emif_clkctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) wait_emif_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	ldr	r2, [r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	mov	r3, #AM33XX_CM_CLKCTRL_MODULESTATE_DISABLED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	cmp	r2, r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	bne	wait_emif_disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) emif_skip_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	tst	r4, #WFI_FLAG_WAKE_M3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	beq	wkup_m3_skip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	 * For the MPU WFI to be registered as an interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	 * to WKUP_M3, MPU_CLKCTRL.MODULEMODE needs to be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	 * to DISABLED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	ldr	r1, virt_mpu_clkctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	ldr	r2, [r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	bic	r2, r2, #AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	str	r2, [r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) wkup_m3_skip:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	 * Execute an ISB instruction to ensure that all of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	 * CP15 register changes have been committed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	 * Execute a barrier instruction to ensure that all cache,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	 * TLB and branch predictor maintenance operations issued
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	 * have completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	dsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	dmb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	 * Execute a WFI instruction and wait until the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	 * STANDBYWFI output is asserted to indicate that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	 * CPU is in idle and low power state. CPU can specualatively
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	 * prefetch the instructions so add NOPs after WFI. Thirteen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	 * NOPs as per Cortex-A8 pipeline.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	wfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	/* We come here in case of an abort due to a late interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	/* Set MPU_CLKCTRL.MODULEMODE back to ENABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	ldr	r1, virt_mpu_clkctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	mov	r2, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	str	r2, [r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	/* Re-enable EMIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	ldr	r1, virt_emif_clkctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	mov	r2, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	str	r2, [r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) wait_emif_enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	ldr	r3, [r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	cmp	r2, r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	bne	wait_emif_enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	/* Only necessary if PER is losing context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	tst	r4, #WFI_FLAG_SELF_REFRESH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	beq	emif_skip_exit_sr_abt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	adr	r9, am33xx_emif_sram_table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	ldr	r1, [r9, #EMIF_PM_ABORT_SR_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	blx	r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) emif_skip_exit_sr_abt:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	tst	r4, #WFI_FLAG_FLUSH_CACHE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	beq	cache_skip_restore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	 * Set SCTLR.C bit to allow data cache allocation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	mrc	p15, 0, r0, c1, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	orr	r0, r0, #(1 << 2)	@ Enable the C bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	mcr	p15, 0, r0, c1, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) cache_skip_restore:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	/* Let the suspend code know about the abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	mov	r0, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	ldmfd	sp!, {r4 - r11, pc}	@ restore regs and return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ENDPROC(am33xx_do_wfi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	.align
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ENTRY(am33xx_resume_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	.word . - am33xx_do_wfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ENTRY(am33xx_resume_from_deep_sleep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	/* Re-enable EMIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	ldr	r0, phys_emif_clkctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	mov	r1, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	str	r1, [r0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) wait_emif_enable1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	ldr	r2, [r0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	cmp	r1, r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	bne	wait_emif_enable1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	adr	r9, am33xx_emif_sram_table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	ldr	r1, [r9, #EMIF_PM_RESTORE_CONTEXT_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	blx	r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	ldr	r1, [r9, #EMIF_PM_EXIT_SR_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	blx	r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) resume_to_ddr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	/* We are back. Branch to the common CPU resume routine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	mov	r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	ldr	pc, resume_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ENDPROC(am33xx_resume_from_deep_sleep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)  * Local variables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	.align
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) kernel_flush:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	.word   v7_flush_dcache_all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) virt_mpu_clkctrl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	.word	AM33XX_CM_MPU_MPU_CLKCTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) virt_emif_clkctrl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	.word	AM33XX_CM_PER_EMIF_CLKCTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) phys_emif_clkctrl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	.word	(AM33XX_CM_BASE + AM33XX_CM_PER_MOD + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .align 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* DDR related defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) am33xx_emif_sram_table:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	.space EMIF_PM_FUNCTIONS_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ENTRY(am33xx_pm_sram)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	.word am33xx_do_wfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	.word am33xx_do_wfi_sz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	.word am33xx_resume_offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	.word am33xx_emif_sram_table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	.word am33xx_pm_ro_sram_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) resume_addr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .word  cpu_resume - PAGE_OFFSET + 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .align 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ENTRY(am33xx_pm_ro_sram_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	.space AMX3_PM_RO_SRAM_DATA_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) ENTRY(am33xx_do_wfi_sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	.word	. - am33xx_do_wfi