^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __ARCH_ARM_MACH_OMAP2_SDRC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __ARCH_ARM_MACH_OMAP2_SDRC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * OMAP2/3 SDRC/SMS macros and prototypes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2007-2008, 2012 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2007-2008 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Paul Walmsley
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Tony Lindgren
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Richard Woodruff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #undef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #ifndef __ASSEMBLER__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) extern void __iomem *omap2_sdrc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) extern void __iomem *omap2_sms_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define OMAP_SDRC_REGADDR(reg) (omap2_sdrc_base + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define OMAP_SMS_REGADDR(reg) (omap2_sms_base + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* SDRC global register get/set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static inline void sdrc_write_reg(u32 val, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) writel_relaxed(val, OMAP_SDRC_REGADDR(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static inline u32 sdrc_read_reg(u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) return readl_relaxed(OMAP_SDRC_REGADDR(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* SMS global register get/set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static inline void sms_write_reg(u32 val, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) writel_relaxed(val, OMAP_SMS_REGADDR(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static inline u32 sms_read_reg(u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return readl_relaxed(OMAP_SMS_REGADDR(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) extern void omap2_set_globals_sdrc(void __iomem *sdrc, void __iomem *sms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @rate: SDRC clock rate (in Hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @mr: Value to program to SDRC_MR for this rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * This structure holds a pre-computed set of register values for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * SDRC for a given SDRC clock rate and SDRAM chip. These are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * intended to be pre-computed and specified in an array in the board-*.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * files. The structure is keyed off the 'rate' field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct omap_sdrc_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 actim_ctrla;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 actim_ctrlb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 rfr_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 mr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #ifdef CONFIG_SOC_HAS_OMAP2_SDRC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) void omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct omap_sdrc_params *sdrc_cs1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static inline void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct omap_sdrc_params *sdrc_cs1) {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int omap2_sdrc_get_params(unsigned long r,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct omap_sdrc_params **sdrc_cs0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct omap_sdrc_params **sdrc_cs1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) void omap2_sms_save_context(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) void omap2_sms_restore_context(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct memory_timings {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 m_type; /* ddr = 1, sdr = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 base_cs; /* base chip select to use for calculations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct omap_sdrc_params *rx51_get_sdram_timings(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 omap2xxx_sdrc_dll_is_unlocked(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define OMAP242X_SDRC_REGADDR(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define OMAP243X_SDRC_REGADDR(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define OMAP34XX_SDRC_REGADDR(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #endif /* __ASSEMBLER__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Minimum frequency that the SDRC DLL can lock at */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MIN_SDRC_DLL_LOCK_FREQ 83000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SDRC_MPURATE_SCALE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SDRC_MPURATE_BASE_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SDRC_MPURATE_LOOPS 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SDRC_SYSCONFIG 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SDRC_CS_CFG 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SDRC_SHARING 0x044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SDRC_ERR_TYPE 0x04C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SDRC_DLLA_CTRL 0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SDRC_DLLA_STATUS 0x064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SDRC_DLLB_CTRL 0x068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SDRC_DLLB_STATUS 0x06C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SDRC_POWER 0x070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SDRC_MCFG_0 0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SDRC_MR_0 0x084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SDRC_EMR2_0 0x08c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SDRC_ACTIM_CTRL_A_0 0x09c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SDRC_ACTIM_CTRL_B_0 0x0a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SDRC_RFR_CTRL_0 0x0a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SDRC_MANUAL_0 0x0a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SDRC_MCFG_1 0x0B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SDRC_MR_1 0x0B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SDRC_EMR2_1 0x0BC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SDRC_ACTIM_CTRL_A_1 0x0C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define SDRC_ACTIM_CTRL_B_1 0x0C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SDRC_RFR_CTRL_1 0x0D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SDRC_MANUAL_1 0x0D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SDRC_POWER_AUTOCOUNT_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SDRC_POWER_AUTOCOUNT_MASK (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SDRC_POWER_CLKCTRL_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SDRC_POWER_CLKCTRL_MASK (0x3 << SDRC_POWER_CLKCTRL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SDRC_SELF_REFRESH_ON_AUTOCOUNT (0x2 << SDRC_POWER_CLKCTRL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * These values represent the number of memory clock cycles between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * rows per device, and include a subtraction of a 50 cycle window in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * event that the autorefresh command is delayed due to other SDRC activity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * The '| 1' sets the ARE field to send one autorefresh when the autorefresh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * counter reaches 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * These represent optimal values for common parts, it won't work for all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * As long as you scale down, most parameters are still work, they just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * become sub-optimal. The RFR value goes in the opposite direction. If you
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * don't adjust it down as your clock period increases the refresh interval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * will not be met. Setting all parameters for complete worst case may work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * but may cut memory performance by 2x. Due to errata the DLLs need to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * unlocked and their value needs run time calibration. A dynamic call is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * need for that as no single right value exists across production samples.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * Only the FULL speed values are given. Current code is such that rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * changes must be made at DPLLoutx2. The actual value adjustment for low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * frequency operation will be handled by omap_set_performance()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * By having the boot loader boot up in the fastest L4 speed available likely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * will result in something which you can switch between.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define SDRC_RFR_CTRL_165MHz (0x00044c00 | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define SDRC_RFR_CTRL_133MHz (0x0003de00 | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define SDRC_RFR_CTRL_100MHz (0x0002da01 | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * SMS register access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define OMAP242X_SMS_REGADDR(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define OMAP243X_SMS_REGADDR(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define OMAP343X_SMS_REGADDR(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* SMS register offsets - read/write with sms_{read,write}_reg() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SMS_SYSCONFIG 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* REVISIT: fill in other SMS registers here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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