^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SMS/SDRC (SDRAM controller) common code for OMAP2/3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2005, 2008 Texas Instruments Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2005, 2008 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Tony Lindgren <tony@atomide.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Paul Walmsley
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Richard Woodruff <r-woodruff2@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #undef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "sdrc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) void __iomem *omap2_sdrc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) void __iomem *omap2_sms_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct omap2_sms_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 sms_sysconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static struct omap2_sms_regs sms_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* SDRC_POWER register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SDRC_POWER_EXTCLKDIS_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SDRC_POWER_PWDENA_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SDRC_POWER_PAGEPOLICY_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * omap2_sms_save_context - Save SMS registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * Save SMS registers that need to be restored after off mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) void omap2_sms_save_context(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) sms_context.sms_sysconfig = sms_read_reg(SMS_SYSCONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * omap2_sms_restore_context - Restore SMS registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * Restore SMS registers that need to be Restored after off mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) void omap2_sms_restore_context(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) sms_write_reg(sms_context.sms_sysconfig, SMS_SYSCONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * omap2_sdrc_get_params - return SDRC register values for a given clock rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * @r: SDRC clock rate (in Hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * @sdrc_cs0: chip select 0 ram timings **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @sdrc_cs1: chip select 1 ram timings **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * Return pre-calculated values for the SDRC_ACTIM_CTRLA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * structs,for a given SDRC clock rate 'r'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * These parameters control various timing delays in the SDRAM controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * that are expressed in terms of the number of SDRC clock cycles to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * wait; hence the clock rate dependency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * Supports 2 different timing parameters for both chip selects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * Note 1: the sdrc_init_params_cs[01] must be sorted rate descending.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * as sdrc_init_params_cs_0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * Fills in the struct omap_sdrc_params * for each chip select.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * Returns 0 upon success or -1 upon failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int omap2_sdrc_get_params(unsigned long r,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct omap_sdrc_params **sdrc_cs0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct omap_sdrc_params **sdrc_cs1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct omap_sdrc_params *sp0, *sp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (!sdrc_init_params_cs0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) sp0 = sdrc_init_params_cs0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) sp1 = sdrc_init_params_cs1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) while (sp0->rate && sp0->rate != r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) sp0++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (sdrc_init_params_cs1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) sp1++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (!sp0->rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) *sdrc_cs0 = sp0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) *sdrc_cs1 = sp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) void __init omap2_set_globals_sdrc(void __iomem *sdrc, void __iomem *sms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) omap2_sdrc_base = sdrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) omap2_sms_base = sms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * omap2_sdrc_init - initialize SMS, SDRC devices on boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * @sdrc_cs[01]: pointers to a null-terminated list of struct omap_sdrc_params
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * Support for 2 chip selects timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * Turn on smart idle modes for SDRAM scheduler and controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * Program a known-good configuration for the SDRC to deal with buggy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * bootloaders.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct omap_sdrc_params *sdrc_cs1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) l = sms_read_reg(SMS_SYSCONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) l &= ~(0x3 << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) l |= (0x2 << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) sms_write_reg(l, SMS_SYSCONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) l = sdrc_read_reg(SDRC_SYSCONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) l &= ~(0x3 << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) l |= (0x2 << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) sdrc_write_reg(l, SDRC_SYSCONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) sdrc_init_params_cs0 = sdrc_cs0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) sdrc_init_params_cs1 = sdrc_cs1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* XXX Enable SRFRONIDLEREQ here also? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * PWDENA should not be set due to 34xx erratum 1.150 - PWDENA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * can cause random memory corruption
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) (1 << SDRC_POWER_PAGEPOLICY_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) sdrc_write_reg(l, SDRC_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) omap2_sms_save_context();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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