Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * OMAP54XX SCRM registers and bitfields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Benoit Cousson (b-cousson@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * This file is automatically generated from the OMAP hardware databases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * We respectfully ask that any modifications to this file be coordinated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * with the public linux-omap@vger.kernel.org mailing list and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * authors above to ensure that the autogeneration scripts are kept
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * up-to-date with the file contents.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #ifndef __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define OMAP5_SCRM_BASE		0x4ae0a000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define OMAP54XX_SCRM_REGADDR(reg)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	OMAP2_L4_IO_ADDRESS(OMAP5_SCRM_BASE + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /* SCRM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /* SCRM.SCRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define OMAP5_SCRM_REVISION_SCRM_OFFSET		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define OMAP5_SCRM_REVISION_SCRM		OMAP54XX_SCRM_REGADDR(0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define OMAP5_SCRM_CLKSETUPTIME_OFFSET		0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define OMAP5_SCRM_CLKSETUPTIME			OMAP54XX_SCRM_REGADDR(0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define OMAP5_SCRM_PMICSETUPTIME_OFFSET		0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define OMAP5_SCRM_PMICSETUPTIME		OMAP54XX_SCRM_REGADDR(0x0104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define OMAP5_SCRM_ALTCLKSRC_OFFSET		0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define OMAP5_SCRM_ALTCLKSRC			OMAP54XX_SCRM_REGADDR(0x0110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define OMAP5_SCRM_MODEMCLKM_OFFSET		0x0118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define OMAP5_SCRM_MODEMCLKM			OMAP54XX_SCRM_REGADDR(0x0118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define OMAP5_SCRM_D2DCLKM_OFFSET		0x011c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define OMAP5_SCRM_D2DCLKM			OMAP54XX_SCRM_REGADDR(0x011c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define OMAP5_SCRM_EXTCLKREQ_OFFSET		0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define OMAP5_SCRM_EXTCLKREQ			OMAP54XX_SCRM_REGADDR(0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define OMAP5_SCRM_ACCCLKREQ_OFFSET		0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define OMAP5_SCRM_ACCCLKREQ			OMAP54XX_SCRM_REGADDR(0x0204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define OMAP5_SCRM_PWRREQ_OFFSET		0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define OMAP5_SCRM_PWRREQ			OMAP54XX_SCRM_REGADDR(0x0208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define OMAP5_SCRM_AUXCLKREQ0_OFFSET		0x0210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define OMAP5_SCRM_AUXCLKREQ0			OMAP54XX_SCRM_REGADDR(0x0210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define OMAP5_SCRM_AUXCLKREQ1_OFFSET		0x0214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define OMAP5_SCRM_AUXCLKREQ1			OMAP54XX_SCRM_REGADDR(0x0214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define OMAP5_SCRM_AUXCLKREQ2_OFFSET		0x0218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define OMAP5_SCRM_AUXCLKREQ2			OMAP54XX_SCRM_REGADDR(0x0218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define OMAP5_SCRM_AUXCLKREQ3_OFFSET		0x021c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define OMAP5_SCRM_AUXCLKREQ3			OMAP54XX_SCRM_REGADDR(0x021c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define OMAP5_SCRM_AUXCLKREQ4_OFFSET		0x0220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define OMAP5_SCRM_AUXCLKREQ4			OMAP54XX_SCRM_REGADDR(0x0220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define OMAP5_SCRM_AUXCLKREQ5_OFFSET		0x0224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define OMAP5_SCRM_AUXCLKREQ5			OMAP54XX_SCRM_REGADDR(0x0224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define OMAP5_SCRM_D2DCLKREQ_OFFSET		0x0234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define OMAP5_SCRM_D2DCLKREQ			OMAP54XX_SCRM_REGADDR(0x0234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define OMAP5_SCRM_AUXCLK0_OFFSET		0x0310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define OMAP5_SCRM_AUXCLK0			OMAP54XX_SCRM_REGADDR(0x0310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define OMAP5_SCRM_AUXCLK1_OFFSET		0x0314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define OMAP5_SCRM_AUXCLK1			OMAP54XX_SCRM_REGADDR(0x0314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define OMAP5_SCRM_AUXCLK2_OFFSET		0x0318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define OMAP5_SCRM_AUXCLK2			OMAP54XX_SCRM_REGADDR(0x0318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define OMAP5_SCRM_AUXCLK3_OFFSET		0x031c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define OMAP5_SCRM_AUXCLK3			OMAP54XX_SCRM_REGADDR(0x031c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define OMAP5_SCRM_AUXCLK4_OFFSET		0x0320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define OMAP5_SCRM_AUXCLK4			OMAP54XX_SCRM_REGADDR(0x0320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define OMAP5_SCRM_AUXCLK5_OFFSET		0x0324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define OMAP5_SCRM_AUXCLK5			OMAP54XX_SCRM_REGADDR(0x0324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define OMAP5_SCRM_RSTTIME_OFFSET		0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define OMAP5_SCRM_RSTTIME			OMAP54XX_SCRM_REGADDR(0x0400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define OMAP5_SCRM_MODEMRSTCTRL_OFFSET		0x0418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define OMAP5_SCRM_MODEMRSTCTRL			OMAP54XX_SCRM_REGADDR(0x0418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define OMAP5_SCRM_D2DRSTCTRL_OFFSET		0x041c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define OMAP5_SCRM_D2DRSTCTRL			OMAP54XX_SCRM_REGADDR(0x041c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define OMAP5_SCRM_EXTPWRONRSTCTRL_OFFSET	0x0420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define OMAP5_SCRM_EXTPWRONRSTCTRL		OMAP54XX_SCRM_REGADDR(0x0420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define OMAP5_SCRM_EXTWARMRSTST_OFFSET		0x0510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define OMAP5_SCRM_EXTWARMRSTST			OMAP54XX_SCRM_REGADDR(0x0510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define OMAP5_SCRM_APEWARMRSTST_OFFSET		0x0514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define OMAP5_SCRM_APEWARMRSTST			OMAP54XX_SCRM_REGADDR(0x0514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define OMAP5_SCRM_MODEMWARMRSTST_OFFSET	0x0518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define OMAP5_SCRM_MODEMWARMRSTST		OMAP54XX_SCRM_REGADDR(0x0518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define OMAP5_SCRM_D2DWARMRSTST_OFFSET		0x051c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define OMAP5_SCRM_D2DWARMRSTST			OMAP54XX_SCRM_REGADDR(0x051c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)  * Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)  * AUXCLKREQ5, D2DCLKREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define OMAP5_ACCURACY_SHIFT			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define OMAP5_ACCURACY_WIDTH			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define OMAP5_ACCURACY_MASK			(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) /* Used by APEWARMRSTST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define OMAP5_APEWARMRSTST_SHIFT		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define OMAP5_APEWARMRSTST_WIDTH		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define OMAP5_APEWARMRSTST_MASK			(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define OMAP5_CLKDIV_SHIFT			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define OMAP5_CLKDIV_WIDTH			0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define OMAP5_CLKDIV_MASK			(0xf << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Used by D2DCLKM, MODEMCLKM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define OMAP5_CLK_32KHZ_SHIFT			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define OMAP5_CLK_32KHZ_WIDTH			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define OMAP5_CLK_32KHZ_MASK			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Used by D2DRSTCTRL, MODEMRSTCTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define OMAP5_COLDRST_SHIFT			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define OMAP5_COLDRST_WIDTH			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define OMAP5_COLDRST_MASK			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Used by D2DWARMRSTST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define OMAP5_D2DWARMRSTST_SHIFT		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define OMAP5_D2DWARMRSTST_WIDTH		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define OMAP5_D2DWARMRSTST_MASK			(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Used by AUXCLK0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define OMAP5_DISABLECLK_SHIFT			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define OMAP5_DISABLECLK_WIDTH			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define OMAP5_DISABLECLK_MASK			(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Used by CLKSETUPTIME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define OMAP5_DOWNTIME_SHIFT			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define OMAP5_DOWNTIME_WIDTH			0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define OMAP5_DOWNTIME_MASK			(0x3f << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define OMAP5_ENABLE_SHIFT			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define OMAP5_ENABLE_WIDTH			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define OMAP5_ENABLE_MASK			(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Renamed from ENABLE Used by EXTPWRONRSTCTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define OMAP5_ENABLE_0_0_SHIFT			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define OMAP5_ENABLE_0_0_WIDTH			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define OMAP5_ENABLE_0_0_MASK			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Used by ALTCLKSRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define OMAP5_ENABLE_EXT_SHIFT			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define OMAP5_ENABLE_EXT_WIDTH			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define OMAP5_ENABLE_EXT_MASK			(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Used by ALTCLKSRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define OMAP5_ENABLE_INT_SHIFT			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define OMAP5_ENABLE_INT_WIDTH			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define OMAP5_ENABLE_INT_MASK			(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Used by EXTWARMRSTST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define OMAP5_EXTWARMRSTST_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define OMAP5_EXTWARMRSTST_WIDTH		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define OMAP5_EXTWARMRSTST_MASK			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)  * Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)  * AUXCLKREQ5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define OMAP5_MAPPING_SHIFT			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define OMAP5_MAPPING_WIDTH			0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define OMAP5_MAPPING_MASK			(0x7 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Used by ALTCLKSRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define OMAP5_MODE_SHIFT			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define OMAP5_MODE_WIDTH			0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define OMAP5_MODE_MASK				(0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Used by MODEMWARMRSTST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define OMAP5_MODEMWARMRSTST_SHIFT		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define OMAP5_MODEMWARMRSTST_WIDTH		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define OMAP5_MODEMWARMRSTST_MASK		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)  * Used by ACCCLKREQ, AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)  * AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4, AUXCLKREQ5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)  * D2DCLKREQ, EXTCLKREQ, PWRREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define OMAP5_POLARITY_SHIFT			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define OMAP5_POLARITY_WIDTH			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define OMAP5_POLARITY_MASK			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Used by EXTPWRONRSTCTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define OMAP5_PWRONRST_SHIFT			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define OMAP5_PWRONRST_WIDTH			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define OMAP5_PWRONRST_MASK			(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Used by REVISION_SCRM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define OMAP5_REV_SHIFT				0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define OMAP5_REV_WIDTH				0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define OMAP5_REV_MASK				(0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* Used by RSTTIME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define OMAP5_RSTTIME_SHIFT			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define OMAP5_RSTTIME_WIDTH			0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define OMAP5_RSTTIME_MASK			(0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* Used by CLKSETUPTIME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define OMAP5_SETUPTIME_SHIFT			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define OMAP5_SETUPTIME_WIDTH			0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define OMAP5_SETUPTIME_MASK			(0xfff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Used by PMICSETUPTIME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define OMAP5_SLEEPTIME_SHIFT			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define OMAP5_SLEEPTIME_WIDTH			0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define OMAP5_SLEEPTIME_MASK			(0x3f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define OMAP5_SRCSELECT_SHIFT			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define OMAP5_SRCSELECT_WIDTH			0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define OMAP5_SRCSELECT_MASK			(0x3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Used by D2DCLKM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define OMAP5_SYSCLK_SHIFT			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define OMAP5_SYSCLK_WIDTH			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define OMAP5_SYSCLK_MASK			(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* Used by PMICSETUPTIME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define OMAP5_WAKEUPTIME_SHIFT			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define OMAP5_WAKEUPTIME_WIDTH			0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define OMAP5_WAKEUPTIME_MASK			(0x3f << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* Used by D2DRSTCTRL, MODEMRSTCTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define OMAP5_WARMRST_SHIFT			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define OMAP5_WARMRST_WIDTH			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define OMAP5_WARMRST_MASK			(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #endif