^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP44xx SCRM registers and bitfields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Benoit Cousson (b-cousson@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This file is automatically generated from the OMAP hardware databases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * We respectfully ask that any modifications to this file be coordinated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * with the public linux-omap@vger.kernel.org mailing list and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * authors above to ensure that the autogeneration scripts are kept
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * up-to-date with the file contents.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #ifndef __ARCH_ARM_MACH_OMAP2_SCRM_44XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define __ARCH_ARM_MACH_OMAP2_SCRM_44XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define OMAP4_SCRM_BASE 0x4a30a000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define OMAP44XX_SCRM_REGADDR(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) OMAP2_L4_IO_ADDRESS(OMAP4_SCRM_BASE + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Registers offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define OMAP4_SCRM_REVISION_SCRM_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define OMAP4_SCRM_REVISION_SCRM OMAP44XX_SCRM_REGADDR(0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define OMAP4_SCRM_CLKSETUPTIME_OFFSET 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define OMAP4_SCRM_CLKSETUPTIME OMAP44XX_SCRM_REGADDR(0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define OMAP4_SCRM_PMICSETUPTIME_OFFSET 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define OMAP4_SCRM_PMICSETUPTIME OMAP44XX_SCRM_REGADDR(0x0104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OMAP4_SCRM_ALTCLKSRC_OFFSET 0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OMAP4_SCRM_ALTCLKSRC OMAP44XX_SCRM_REGADDR(0x0110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OMAP4_SCRM_MODEMCLKM_OFFSET 0x0118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OMAP4_SCRM_MODEMCLKM OMAP44XX_SCRM_REGADDR(0x0118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OMAP4_SCRM_D2DCLKM_OFFSET 0x011c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OMAP4_SCRM_D2DCLKM OMAP44XX_SCRM_REGADDR(0x011c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OMAP4_SCRM_EXTCLKREQ_OFFSET 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OMAP4_SCRM_EXTCLKREQ OMAP44XX_SCRM_REGADDR(0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OMAP4_SCRM_ACCCLKREQ_OFFSET 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define OMAP4_SCRM_ACCCLKREQ OMAP44XX_SCRM_REGADDR(0x0204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OMAP4_SCRM_PWRREQ_OFFSET 0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OMAP4_SCRM_PWRREQ OMAP44XX_SCRM_REGADDR(0x0208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OMAP4_SCRM_AUXCLKREQ0_OFFSET 0x0210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OMAP4_SCRM_AUXCLKREQ0 OMAP44XX_SCRM_REGADDR(0x0210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OMAP4_SCRM_AUXCLKREQ1_OFFSET 0x0214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OMAP4_SCRM_AUXCLKREQ1 OMAP44XX_SCRM_REGADDR(0x0214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OMAP4_SCRM_AUXCLKREQ2_OFFSET 0x0218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OMAP4_SCRM_AUXCLKREQ2 OMAP44XX_SCRM_REGADDR(0x0218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OMAP4_SCRM_AUXCLKREQ3_OFFSET 0x021c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OMAP4_SCRM_AUXCLKREQ3 OMAP44XX_SCRM_REGADDR(0x021c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OMAP4_SCRM_AUXCLKREQ4_OFFSET 0x0220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OMAP4_SCRM_AUXCLKREQ4 OMAP44XX_SCRM_REGADDR(0x0220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OMAP4_SCRM_AUXCLKREQ5_OFFSET 0x0224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OMAP4_SCRM_AUXCLKREQ5 OMAP44XX_SCRM_REGADDR(0x0224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OMAP4_SCRM_D2DCLKREQ_OFFSET 0x0234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OMAP4_SCRM_D2DCLKREQ OMAP44XX_SCRM_REGADDR(0x0234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OMAP4_SCRM_AUXCLK0_OFFSET 0x0310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OMAP4_SCRM_AUXCLK0 OMAP44XX_SCRM_REGADDR(0x0310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OMAP4_SCRM_AUXCLK1_OFFSET 0x0314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OMAP4_SCRM_AUXCLK1 OMAP44XX_SCRM_REGADDR(0x0314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OMAP4_SCRM_AUXCLK2_OFFSET 0x0318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OMAP4_SCRM_AUXCLK2 OMAP44XX_SCRM_REGADDR(0x0318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OMAP4_SCRM_AUXCLK3_OFFSET 0x031c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OMAP4_SCRM_AUXCLK3 OMAP44XX_SCRM_REGADDR(0x031c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OMAP4_SCRM_AUXCLK4_OFFSET 0x0320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OMAP4_SCRM_AUXCLK4 OMAP44XX_SCRM_REGADDR(0x0320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OMAP4_SCRM_AUXCLK5_OFFSET 0x0324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OMAP4_SCRM_AUXCLK5 OMAP44XX_SCRM_REGADDR(0x0324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OMAP4_SCRM_RSTTIME_OFFSET 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OMAP4_SCRM_RSTTIME OMAP44XX_SCRM_REGADDR(0x0400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OMAP4_SCRM_MODEMRSTCTRL_OFFSET 0x0418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OMAP4_SCRM_MODEMRSTCTRL OMAP44XX_SCRM_REGADDR(0x0418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OMAP4_SCRM_D2DRSTCTRL_OFFSET 0x041c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OMAP4_SCRM_D2DRSTCTRL OMAP44XX_SCRM_REGADDR(0x041c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OMAP4_SCRM_EXTPWRONRSTCTRL_OFFSET 0x0420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OMAP4_SCRM_EXTPWRONRSTCTRL OMAP44XX_SCRM_REGADDR(0x0420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define OMAP4_SCRM_EXTWARMRSTST_OFFSET 0x0510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OMAP4_SCRM_EXTWARMRSTST OMAP44XX_SCRM_REGADDR(0x0510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OMAP4_SCRM_APEWARMRSTST_OFFSET 0x0514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OMAP4_SCRM_APEWARMRSTST OMAP44XX_SCRM_REGADDR(0x0514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OMAP4_SCRM_MODEMWARMRSTST_OFFSET 0x0518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OMAP4_SCRM_MODEMWARMRSTST OMAP44XX_SCRM_REGADDR(0x0518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OMAP4_SCRM_D2DWARMRSTST_OFFSET 0x051c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OMAP4_SCRM_D2DWARMRSTST OMAP44XX_SCRM_REGADDR(0x051c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Registers shifts and masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* REVISION_SCRM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define OMAP4_REV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define OMAP4_REV_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* CLKSETUPTIME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define OMAP4_DOWNTIME_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define OMAP4_DOWNTIME_MASK (0x3f << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define OMAP4_SETUPTIME_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define OMAP4_SETUPTIME_MASK (0xfff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* PMICSETUPTIME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define OMAP4_WAKEUPTIME_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define OMAP4_WAKEUPTIME_MASK (0x3f << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define OMAP4_SLEEPTIME_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define OMAP4_SLEEPTIME_MASK (0x3f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* ALTCLKSRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define OMAP4_ENABLE_EXT_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define OMAP4_ENABLE_EXT_MASK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define OMAP4_ENABLE_INT_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define OMAP4_ENABLE_INT_MASK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define OMAP4_ALTCLKSRC_MODE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define OMAP4_ALTCLKSRC_MODE_MASK (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* MODEMCLKM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define OMAP4_CLK_32KHZ_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define OMAP4_CLK_32KHZ_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* D2DCLKM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define OMAP4_SYSCLK_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define OMAP4_SYSCLK_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* EXTCLKREQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define OMAP4_POLARITY_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define OMAP4_POLARITY_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* AUXCLKREQ0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define OMAP4_MAPPING_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define OMAP4_MAPPING_MASK (0x7 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define OMAP4_MAPPING_WIDTH 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define OMAP4_ACCURACY_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define OMAP4_ACCURACY_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* AUXCLK0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define OMAP4_CLKDIV_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define OMAP4_CLKDIV_MASK (0xf << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define OMAP4_CLKDIV_WIDTH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define OMAP4_DISABLECLK_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define OMAP4_DISABLECLK_MASK (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define OMAP4_ENABLE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define OMAP4_ENABLE_MASK (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define OMAP4_SRCSELECT_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define OMAP4_SRCSELECT_MASK (0x3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* RSTTIME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define OMAP4_RSTTIME_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define OMAP4_RSTTIME_MASK (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* MODEMRSTCTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define OMAP4_WARMRST_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define OMAP4_WARMRST_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define OMAP4_COLDRST_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define OMAP4_COLDRST_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* EXTPWRONRSTCTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define OMAP4_PWRONRST_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define OMAP4_PWRONRST_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define OMAP4_ENABLE_EXTPWRONRSTCTRL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define OMAP4_ENABLE_EXTPWRONRSTCTRL_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* EXTWARMRSTST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define OMAP4_EXTWARMRSTST_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define OMAP4_EXTWARMRSTST_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* APEWARMRSTST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define OMAP4_APEWARMRSTST_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define OMAP4_APEWARMRSTST_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* MODEMWARMRSTST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define OMAP4_MODEMWARMRSTST_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define OMAP4_MODEMWARMRSTST_MASK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* D2DWARMRSTST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define OMAP4_D2DWARMRSTST_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define OMAP4_D2DWARMRSTST_MASK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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