^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP4 PRM instance functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2011 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Paul Walmsley
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "iomap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "prcm-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "prm44xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "prm54xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "prm7xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "prminst44xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "prm-regbits-44xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "prcm44xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "prcm43xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "prcm_mpu44xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static struct omap_domain_base _prm_bases[OMAP4_MAX_PRCM_PARTITIONS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static s32 prm_dev_inst = PRM_INSTANCE_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * omap_prm_base_init - Populates the prm partitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Populates the base addresses of the _prm_bases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * array used for read/write of prm module registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) void omap_prm_base_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) memcpy(&_prm_bases[OMAP4430_PRM_PARTITION], &prm_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) sizeof(prm_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) memcpy(&_prm_bases[OMAP4430_PRCM_MPU_PARTITION], &prcm_mpu_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) sizeof(prcm_mpu_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) s32 omap4_prmst_get_prm_dev_inst(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return prm_dev_inst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) void omap4_prminst_set_prm_dev_inst(s32 dev_inst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) prm_dev_inst = dev_inst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Read a register in a PRM instance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) part == OMAP4430_INVALID_PRCM_PARTITION ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) !_prm_bases[part].va);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return readl_relaxed(_prm_bases[part].va + inst + idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Write into a register in a PRM instance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) part == OMAP4430_INVALID_PRCM_PARTITION ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) !_prm_bases[part].va);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) writel_relaxed(val, _prm_bases[part].va + inst + idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Read-modify-write a register in PRM. Caller must lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u16 idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) v = omap4_prminst_read_inst_reg(part, inst, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) v &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) v |= bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) omap4_prminst_write_inst_reg(v, part, inst, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * omap4_prminst_is_hardreset_asserted - read the HW reset line state of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * submodules contained in the hwmod module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * @rstctrl_reg: RM_RSTCTRL register address for this module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * @shift: register bit shift corresponding to the reset line to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * Returns 1 if the (sub)module hardreset line is currently asserted,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * 0 if the (sub)module hardreset line is not currently asserted, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * -EINVAL upon parameter error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u16 rstctrl_offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) v = omap4_prminst_read_inst_reg(part, inst, rstctrl_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) v &= 1 << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) v >>= shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * omap4_prminst_assert_hardreset - assert the HW reset line of a submodule
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * @rstctrl_reg: RM_RSTCTRL register address for this module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @shift: register bit shift corresponding to the reset line to assert
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * Some IPs like dsp, ipu or iva contain processors that require an HW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * reset line to be asserted / deasserted in order to fully enable the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * IP. These modules may have multiple hard-reset lines that reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * different 'submodules' inside the IP block. This function will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * place the submodule into reset. Returns 0 upon success or -EINVAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * upon an argument error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u16 rstctrl_offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 mask = 1 << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) omap4_prminst_rmw_inst_reg_bits(mask, mask, part, inst, rstctrl_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * @shift: register bit shift corresponding to the reset line to deassert
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * @st_shift: status bit offset corresponding to the reset line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * @part: PRM partition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * @inst: PRM instance offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * @rstctrl_offs: reset register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * @rstst_offs: reset status register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * Some IPs like dsp, ipu or iva contain processors that require an HW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * reset line to be asserted / deasserted in order to fully enable the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * IP. These modules may have multiple hard-reset lines that reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * different 'submodules' inside the IP block. This function will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * take the submodule out of reset and wait until the PRCM indicates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * that the reset has completed before returning. Returns 0 upon success or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * -EINVAL upon an argument error, -EEXIST if the submodule was already out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * of reset, or -EBUSY if the submodule did not exit reset promptly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 inst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u16 rstctrl_offs, u16 rstst_offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 mask = 1 << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u32 st_mask = 1 << st_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Check the current status to avoid de-asserting the line twice */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (omap4_prminst_is_hardreset_asserted(shift, part, inst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) rstctrl_offs) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return -EEXIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Clear the reset status by writing 1 to the status bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) omap4_prminst_rmw_inst_reg_bits(0xffffffff, st_mask, part, inst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) rstst_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* de-assert the reset control line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* wait the status to be set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) omap_test_timeout(omap4_prminst_is_hardreset_asserted(st_shift, part,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) inst, rstst_offs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) MAX_MODULE_HARDRESET_WAIT, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) void omap4_prminst_global_warm_sw_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) s32 inst = omap4_prmst_get_prm_dev_inst();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (inst == PRM_INSTANCE_UNKNOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, inst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) OMAP4_PRM_RSTCTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) inst, OMAP4_PRM_RSTCTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* OCP barrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) inst, OMAP4_PRM_RSTCTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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