^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP2+ common Power & Reset Management (PRM) IP block functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2011 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Tero Kristo <t-kristo@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * For historical purposes, the API used to configure the PRM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * interrupt handler refers to it as the "PRCM interrupt." The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * underlying registers are located in the PRM on OMAP3/4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * XXX This code should eventually be moved to a PRM driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/clk/ti.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "prm2xxx_3xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "prm2xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "prm3xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "prm33xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "prm44xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "prm54xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "prm7xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "prcm43xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include "clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include "cm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include "control.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * XXX this is technically not needed, since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * omap_prcm_register_chain_handler() could allocate this based on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * actual amount of memory needed for the SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OMAP_PRCM_MAX_NR_PENDING_REG 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * prcm_irq_chips: an array of all of the "generic IRQ chips" in use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * by the PRCM interrupt handler code. There will be one 'chip' per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * PRM_{IRQSTATUS,IRQENABLE}_MPU register pair. (So OMAP3 will have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * one "chip" and OMAP4 will have two.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static struct irq_chip_generic **prcm_irq_chips;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * prcm_irq_setup: the PRCM IRQ parameters for the hardware the code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * is currently running on. Defined and passed by initialization code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * that calls omap_prcm_register_chain_handler().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static struct omap_prcm_irq_setup *prcm_irq_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* prm_base: base virtual address of the PRM IP block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct omap_domain_base prm_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u16 prm_features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * prm_ll_data: function pointers to SoC-specific implementations of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * common PRM functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static struct prm_ll_data null_prm_ll_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static struct prm_ll_data *prm_ll_data = &null_prm_ll_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Private functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * Move priority events from events to priority_events array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static void omap_prcm_events_filter_priority(unsigned long *events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned long *priority_events)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) priority_events[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) events[i] & prcm_irq_setup->priority_mask[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) events[i] ^= priority_events[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * PRCM Interrupt Handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * This is a common handler for the OMAP PRCM interrupts. Pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * interrupts are detected by a call to prcm_pending_events and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * dispatched accordingly. Clearing of the wakeup events should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * done by the SoC specific individual handlers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void omap_prcm_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned long pending[OMAP_PRCM_MAX_NR_PENDING_REG];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned int virtirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int nr_irq = prcm_irq_setup->nr_regs * 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * If we are suspended, mask all interrupts from PRCM level,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * this does not ack them, and they will be pending until we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * re-enable the interrupts, at which point the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * omap_prcm_irq_handler will be executed again. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * _save_and_clear_irqen() function must ensure that the PRM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * write to disable all IRQs has reached the PRM before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * returning, or spurious PRCM interrupts may occur during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (prcm_irq_setup->suspended) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) prcm_irq_setup->save_and_clear_irqen(prcm_irq_setup->saved_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) prcm_irq_setup->suspend_save_flag = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * Loop until all pending irqs are handled, since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * generic_handle_irq() can cause new irqs to come
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) while (!prcm_irq_setup->suspended) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) prcm_irq_setup->read_pending_irqs(pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* No bit set, then all IRQs are handled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (find_first_bit(pending, nr_irq) >= nr_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) omap_prcm_events_filter_priority(pending, priority_pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * Loop on all currently pending irqs so that new irqs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * cannot starve previously pending irqs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Serve priority events first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) for_each_set_bit(virtirq, priority_pending, nr_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Serve normal events next */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) for_each_set_bit(virtirq, pending, nr_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (chip->irq_ack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) chip->irq_ack(&desc->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (chip->irq_eoi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) chip->irq_eoi(&desc->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) chip->irq_unmask(&desc->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) prcm_irq_setup->ocp_barrier(); /* avoid spurious IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Public functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * omap_prcm_event_to_irq - given a PRCM event name, returns the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * corresponding IRQ on which the handler should be registered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * @name: name of the PRCM interrupt bit to look up - see struct omap_prcm_irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * Returns the Linux internal IRQ ID corresponding to @name upon success,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * or -ENOENT upon failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int omap_prcm_event_to_irq(const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (!prcm_irq_setup || !name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) for (i = 0; i < prcm_irq_setup->nr_irqs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (!strcmp(prcm_irq_setup->irqs[i].name, name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return prcm_irq_setup->base_irq +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) prcm_irq_setup->irqs[i].offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * omap_prcm_irq_cleanup - reverses memory allocated and other steps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * done by omap_prcm_register_chain_handler()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) void omap_prcm_irq_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (!prcm_irq_setup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) pr_err("PRCM: IRQ handler not initialized; cannot cleanup\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (prcm_irq_chips) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (prcm_irq_chips[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) irq_remove_generic_chip(prcm_irq_chips[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 0xffffffff, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) prcm_irq_chips[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) kfree(prcm_irq_chips);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) prcm_irq_chips = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) kfree(prcm_irq_setup->saved_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) prcm_irq_setup->saved_mask = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) kfree(prcm_irq_setup->priority_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) prcm_irq_setup->priority_mask = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) irq = prcm_irq_setup->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) irq_set_chained_handler(irq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (prcm_irq_setup->base_irq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) irq_free_descs(prcm_irq_setup->base_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) prcm_irq_setup->nr_regs * 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) prcm_irq_setup->base_irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) void omap_prcm_irq_prepare(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) prcm_irq_setup->suspended = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) void omap_prcm_irq_complete(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) prcm_irq_setup->suspended = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* If we have not saved the masks, do not attempt to restore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (!prcm_irq_setup->suspend_save_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) prcm_irq_setup->suspend_save_flag = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * Re-enable all masked PRCM irq sources, this causes the PRCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * interrupt to fire immediately if the events were masked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * previously in the chain handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) prcm_irq_setup->restore_irqen(prcm_irq_setup->saved_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * omap_prcm_register_chain_handler - initializes the prcm chained interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * handler based on provided parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * @irq_setup: hardware data about the underlying PRM/PRCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * Set up the PRCM chained interrupt handler on the PRCM IRQ. Sets up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * one generic IRQ chip per PRM interrupt status/enable register pair.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * Returns 0 upon success, -EINVAL if called twice or if invalid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * arguments are passed, or -ENOMEM on any other error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int nr_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int offset, i, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct irq_chip_type *ct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (!irq_setup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) nr_regs = irq_setup->nr_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (prcm_irq_setup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) pr_err("PRCM: already initialized; won't reinitialize\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (nr_regs > OMAP_PRCM_MAX_NR_PENDING_REG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) pr_err("PRCM: nr_regs too large\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) prcm_irq_setup = irq_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) prcm_irq_chips = kcalloc(nr_regs, sizeof(void *), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) prcm_irq_setup->saved_mask = kcalloc(nr_regs, sizeof(u32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) prcm_irq_setup->priority_mask = kcalloc(nr_regs, sizeof(u32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (!prcm_irq_chips || !prcm_irq_setup->saved_mask ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) !prcm_irq_setup->priority_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) memset(mask, 0, sizeof(mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) for (i = 0; i < irq_setup->nr_irqs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) offset = irq_setup->irqs[i].offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) mask[offset >> 5] |= 1 << (offset & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (irq_setup->irqs[i].priority)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) irq_setup->priority_mask[offset >> 5] |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 1 << (offset & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) irq = irq_setup->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) irq_set_chained_handler(irq, omap_prcm_irq_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) irq_setup->base_irq = irq_alloc_descs(-1, 0, irq_setup->nr_regs * 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (irq_setup->base_irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) pr_err("PRCM: failed to allocate irq descs: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) irq_setup->base_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) for (i = 0; i < irq_setup->nr_regs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) gc = irq_alloc_generic_chip("PRCM", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) irq_setup->base_irq + i * 32, prm_base.va,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (!gc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) pr_err("PRCM: failed to allocate generic chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ct = gc->chip_types;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ct->chip.irq_ack = irq_gc_ack_set_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ct->chip.irq_mask = irq_gc_mask_clr_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ct->chip.irq_unmask = irq_gc_mask_set_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ct->regs.ack = irq_setup->ack + i * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ct->regs.mask = irq_setup->mask + i * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) irq_setup_generic_chip(gc, mask[i], 0, IRQ_NOREQUEST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) prcm_irq_chips[i] = gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) irq = omap_prcm_event_to_irq("io");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) omap_pcs_legacy_init(irq, irq_setup->reconfigure_io_chain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) omap_prcm_irq_cleanup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * omap2_set_globals_prm - set the PRM base address (for early use)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * @prm: PRM base virtual address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * XXX Will be replaced when the PRM/CM drivers are completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) void __init omap2_set_globals_prm(void __iomem *prm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) prm_base.va = prm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * prm_read_reset_sources - return the sources of the SoC's last reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * Return a u32 bitmask representing the reset sources that caused the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * SoC to reset. The low-level per-SoC functions called by this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * function remap the SoC-specific reset source bits into an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * OMAP-common set of reset source bits, defined in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * arch/arm/mach-omap2/prm.h. Returns the standardized reset source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * u32 bitmask from the hardware upon success, or returns (1 <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * OMAP_UNKNOWN_RST_SRC_ID_SHIFT) if no low-level read_reset_sources()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * function was registered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) u32 prm_read_reset_sources(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) u32 ret = 1 << OMAP_UNKNOWN_RST_SRC_ID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (prm_ll_data->read_reset_sources)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ret = prm_ll_data->read_reset_sources();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) WARN_ONCE(1, "prm: %s: no mapping function defined for reset sources\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * prm_was_any_context_lost_old - was device context lost? (old API)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * @idx: CONTEXT register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * Return 1 if any bits were set in the *_CONTEXT_* register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * identified by (@part, @inst, @idx), which means that some context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * was lost for that module; otherwise, return 0. XXX Deprecated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * callers need to use a less-SoC-dependent way to identify hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * IP blocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) bool prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) bool ret = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (prm_ll_data->was_any_context_lost_old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ret = prm_ll_data->was_any_context_lost_old(part, inst, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) WARN_ONCE(1, "prm: %s: no mapping function defined\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * prm_clear_context_lost_flags_old - clear context loss flags (old API)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * @idx: CONTEXT register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * Clear hardware context loss bits for the module identified by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * (@part, @inst, @idx). No return value. XXX Deprecated; callers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * need to use a less-SoC-dependent way to identify hardware IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * blocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (prm_ll_data->clear_context_loss_flags_old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) prm_ll_data->clear_context_loss_flags_old(part, inst, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) WARN_ONCE(1, "prm: %s: no mapping function defined\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * omap_prm_assert_hardreset - assert hardreset for an IP block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * @shift: register bit shift corresponding to the reset line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * @part: PRM partition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * @prm_mod: PRM submodule base or instance offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * @offset: register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * Asserts a hardware reset line for an IP block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) int omap_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod, u16 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (!prm_ll_data->assert_hardreset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) WARN_ONCE(1, "prm: %s: no mapping function defined\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return prm_ll_data->assert_hardreset(shift, part, prm_mod, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * omap_prm_deassert_hardreset - deassert hardreset for an IP block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * @shift: register bit shift corresponding to the reset line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * @st_shift: reset status bit shift corresponding to the reset line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * @part: PRM partition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * @prm_mod: PRM submodule base or instance offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * @offset: register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * @st_offset: status register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * Deasserts a hardware reset line for an IP block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int omap_prm_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 prm_mod,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) u16 offset, u16 st_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (!prm_ll_data->deassert_hardreset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) WARN_ONCE(1, "prm: %s: no mapping function defined\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return prm_ll_data->deassert_hardreset(shift, st_shift, part, prm_mod,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) offset, st_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * omap_prm_is_hardreset_asserted - check the hardreset status for an IP block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * @shift: register bit shift corresponding to the reset line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * @part: PRM partition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * @prm_mod: PRM submodule base or instance offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * @offset: register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * Checks if a hardware reset line for an IP block is enabled or not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) int omap_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (!prm_ll_data->is_hardreset_asserted) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) WARN_ONCE(1, "prm: %s: no mapping function defined\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return prm_ll_data->is_hardreset_asserted(shift, part, prm_mod, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * omap_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * Clear any previously-latched I/O wakeup events and ensure that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * I/O wakeup gates are aligned with the current mux settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * Calls SoC specific I/O chain reconfigure function if available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * otherwise does nothing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) void omap_prm_reconfigure_io_chain(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (!prcm_irq_setup || !prcm_irq_setup->reconfigure_io_chain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) prcm_irq_setup->reconfigure_io_chain();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * omap_prm_reset_system - trigger global SW reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * Triggers SoC specific global warm reset to reboot the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) void omap_prm_reset_system(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (!prm_ll_data->reset_system) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) WARN_ONCE(1, "prm: %s: no mapping function defined\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) prm_ll_data->reset_system();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) wfe();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * omap_prm_clear_mod_irqs - clear wake-up events from PRCM interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * @module: PRM module to clear wakeups from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * @regs: register to clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * @wkst_mask: wkst bits to clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * Clears any wakeup events for the module and register set defined.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * Uses SoC specific implementation to do the actual wakeup status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * clearing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) int omap_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (!prm_ll_data->clear_mod_irqs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) WARN_ONCE(1, "prm: %s: no mapping function defined\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return prm_ll_data->clear_mod_irqs(module, regs, wkst_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * omap_prm_vp_check_txdone - check voltage processor TX done status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * Checks if voltage processor transmission has been completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * Returns non-zero if a transmission has completed, 0 otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) u32 omap_prm_vp_check_txdone(u8 vp_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (!prm_ll_data->vp_check_txdone) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) WARN_ONCE(1, "prm: %s: no mapping function defined\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return prm_ll_data->vp_check_txdone(vp_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * omap_prm_vp_clear_txdone - clears voltage processor TX done status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * Clears the status bit for completed voltage processor transmission
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * returned by prm_vp_check_txdone.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) void omap_prm_vp_clear_txdone(u8 vp_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (!prm_ll_data->vp_clear_txdone) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) WARN_ONCE(1, "prm: %s: no mapping function defined\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) prm_ll_data->vp_clear_txdone(vp_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * prm_register - register per-SoC low-level data with the PRM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * @pld: low-level per-SoC OMAP PRM data & function pointers to register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * Register per-SoC low-level OMAP PRM data and function pointers with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * the OMAP PRM common interface. The caller must keep the data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * pointed to by @pld valid until it calls prm_unregister() and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * it returns successfully. Returns 0 upon success, -EINVAL if @pld
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * is NULL, or -EEXIST if prm_register() has already been called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * without an intervening prm_unregister().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) int prm_register(struct prm_ll_data *pld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (!pld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (prm_ll_data != &null_prm_ll_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return -EEXIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) prm_ll_data = pld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * prm_unregister - unregister per-SoC low-level data & function pointers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * @pld: low-level per-SoC OMAP PRM data & function pointers to unregister
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * Unregister per-SoC low-level OMAP PRM data and function pointers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * that were previously registered with prm_register(). The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * caller may not destroy any of the data pointed to by @pld until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * this function returns successfully. Returns 0 upon success, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * -EINVAL if @pld is NULL or if @pld does not match the struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * prm_ll_data * previously registered by prm_register().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) int prm_unregister(struct prm_ll_data *pld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (!pld || prm_ll_data != pld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) prm_ll_data = &null_prm_ll_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #ifdef CONFIG_ARCH_OMAP2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static struct omap_prcm_init_data omap2_prm_data __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .index = TI_CLKM_PRM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .init = omap2xxx_prm_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #ifdef CONFIG_ARCH_OMAP3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static struct omap_prcm_init_data omap3_prm_data __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .index = TI_CLKM_PRM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .init = omap3xxx_prm_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * IVA2 offset is a negative value, must offset the prm_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * address by this to get it to positive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .offset = -OMAP3430_IVA2_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_TI81XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static struct omap_prcm_init_data am3_prm_data __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .index = TI_CLKM_PRM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .init = am33xx_prm_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #ifdef CONFIG_SOC_TI81XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static struct omap_prcm_init_data dm814_pllss_data __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .index = TI_CLKM_PLLSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .init = am33xx_prm_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #ifdef CONFIG_ARCH_OMAP4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static struct omap_prcm_init_data omap4_prm_data __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .index = TI_CLKM_PRM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .init = omap44xx_prm_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .device_inst_offset = OMAP4430_PRM_DEVICE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .flags = PRM_HAS_IO_WAKEUP | PRM_HAS_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #ifdef CONFIG_SOC_OMAP5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static struct omap_prcm_init_data omap5_prm_data __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .index = TI_CLKM_PRM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .init = omap44xx_prm_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .device_inst_offset = OMAP54XX_PRM_DEVICE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .flags = PRM_HAS_IO_WAKEUP | PRM_HAS_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #ifdef CONFIG_SOC_DRA7XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static struct omap_prcm_init_data dra7_prm_data __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .index = TI_CLKM_PRM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .init = omap44xx_prm_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .device_inst_offset = DRA7XX_PRM_DEVICE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .flags = PRM_HAS_IO_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #ifdef CONFIG_SOC_AM43XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static struct omap_prcm_init_data am4_prm_data __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .index = TI_CLKM_PRM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .init = omap44xx_prm_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .device_inst_offset = AM43XX_PRM_DEVICE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .flags = PRM_HAS_IO_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static struct omap_prcm_init_data scrm_data __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .index = TI_CLKM_SCRM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static const struct of_device_id omap_prcm_dt_match_table[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #ifdef CONFIG_SOC_AM33XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) { .compatible = "ti,am3-prcm", .data = &am3_prm_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #ifdef CONFIG_SOC_AM43XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) { .compatible = "ti,am4-prcm", .data = &am4_prm_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #ifdef CONFIG_SOC_TI81XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) { .compatible = "ti,dm814-prcm", .data = &am3_prm_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) { .compatible = "ti,dm814-pllss", .data = &dm814_pllss_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) { .compatible = "ti,dm816-prcm", .data = &am3_prm_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #ifdef CONFIG_ARCH_OMAP2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) { .compatible = "ti,omap2-prcm", .data = &omap2_prm_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #ifdef CONFIG_ARCH_OMAP3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) { .compatible = "ti,omap3-prm", .data = &omap3_prm_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #ifdef CONFIG_ARCH_OMAP4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) { .compatible = "ti,omap4-prm", .data = &omap4_prm_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) { .compatible = "ti,omap4-scrm", .data = &scrm_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #ifdef CONFIG_SOC_OMAP5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) { .compatible = "ti,omap5-prm", .data = &omap5_prm_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) { .compatible = "ti,omap5-scrm", .data = &scrm_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #ifdef CONFIG_SOC_DRA7XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) { .compatible = "ti,dra7-prm", .data = &dra7_prm_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * omap2_prm_base_init - initialize iomappings for the PRM driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * Detects and initializes the iomappings for the PRM driver, based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * on the DT data. Returns 0 in success, negative error value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) int __init omap2_prm_base_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) struct omap_prcm_init_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) for_each_matching_node_and_match(np, omap_prcm_dt_match_table, &match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) data = (struct omap_prcm_init_data *)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) ret = of_address_to_resource(np, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) data->mem = ioremap(res.start, resource_size(&res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (data->index == TI_CLKM_PRM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) prm_base.va = data->mem + data->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) prm_base.pa = res.start + data->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) data->np = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (data->init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) data->init(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) int __init omap2_prcm_base_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) ret = omap2_prm_base_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return omap2_cm_base_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * omap_prcm_init - low level init for the PRCM drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * Initializes the low level clock infrastructure for PRCM drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) * Returns 0 in success, negative error value in failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) int __init omap_prcm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) const struct omap_prcm_init_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) for_each_matching_node_and_match(np, omap_prcm_dt_match_table, &match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) data = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) ret = omap2_clk_provider_init(np, data->index, NULL, data->mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) omap_cm_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static int __init prm_late_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (prm_ll_data->late_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return prm_ll_data->late_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) subsys_initcall(prm_late_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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