^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * DRA7xx PRM instance offset macros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Generated by code originally written by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Paul Walmsley (paul@pwsan.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Rajendra Nayak (rnayak@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Benoit Cousson (b-cousson@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * This file is automatically generated from the OMAP hardware databases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * We respectfully ask that any modifications to this file be coordinated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * with the public linux-omap@vger.kernel.org mailing list and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * authors above to ensure that the autogeneration scripts are kept
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * up-to-date with the file contents.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #ifndef __ARCH_ARM_MACH_OMAP2_PRM7XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define __ARCH_ARM_MACH_OMAP2_PRM7XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "prcm-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "prm44xx_54xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "prm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DRA7XX_PRM_BASE 0x4ae06000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DRA7XX_PRM_REGADDR(inst, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) OMAP2_L4_IO_ADDRESS(DRA7XX_PRM_BASE + (inst) + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* PRM instances */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DRA7XX_PRM_OCP_SOCKET_INST 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DRA7XX_PRM_CKGEN_INST 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DRA7XX_PRM_MPU_INST 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DRA7XX_PRM_DSP1_INST 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DRA7XX_PRM_IPU_INST 0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DRA7XX_PRM_COREAON_INST 0x0628
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DRA7XX_PRM_CORE_INST 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DRA7XX_PRM_IVA_INST 0x0f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DRA7XX_PRM_CAM_INST 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DRA7XX_PRM_DSS_INST 0x1100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DRA7XX_PRM_GPU_INST 0x1200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DRA7XX_PRM_L3INIT_INST 0x1300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DRA7XX_PRM_L4PER_INST 0x1400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DRA7XX_PRM_CUSTEFUSE_INST 0x1600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DRA7XX_PRM_WKUPAON_INST 0x1724
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DRA7XX_PRM_WKUPAON_CM_INST 0x1800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DRA7XX_PRM_EMU_INST 0x1900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DRA7XX_PRM_EMU_CM_INST 0x1a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DRA7XX_PRM_DSP2_INST 0x1b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DRA7XX_PRM_EVE1_INST 0x1b40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DRA7XX_PRM_EVE2_INST 0x1b80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DRA7XX_PRM_EVE3_INST 0x1bc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DRA7XX_PRM_EVE4_INST 0x1c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DRA7XX_PRM_RTC_INST 0x1c60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DRA7XX_PRM_VPE_INST 0x1c80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DRA7XX_PRM_DEVICE_INST 0x1d00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DRA7XX_PRM_INSTR_INST 0x1f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* PRM clockdomain register offsets (from instance start) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DRA7XX_PRM_EMU_CM_EMU_CDOFFS 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* PRM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* PRM.OCP_SOCKET_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DRA7XX_REVISION_PRM_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DRA7XX_PRM_IRQSTATUS_MPU_OFFSET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DRA7XX_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DRA7XX_PRM_IRQENABLE_MPU_OFFSET 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DRA7XX_PRM_IRQENABLE_MPU_2_OFFSET 0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DRA7XX_PRM_IRQSTATUS_IPU2_OFFSET 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DRA7XX_PRM_IRQENABLE_IPU2_OFFSET 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DRA7XX_PRM_IRQSTATUS_DSP1_OFFSET 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DRA7XX_PRM_IRQENABLE_DSP1_OFFSET 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DRA7XX_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DRA7XX_CM_PRM_PROFILING_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_OCP_SOCKET_INST, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DRA7XX_PRM_IRQENABLE_DSP2_OFFSET 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DRA7XX_PRM_IRQENABLE_EVE1_OFFSET 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DRA7XX_PRM_IRQENABLE_EVE2_OFFSET 0x004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DRA7XX_PRM_IRQENABLE_EVE3_OFFSET 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DRA7XX_PRM_IRQENABLE_EVE4_OFFSET 0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DRA7XX_PRM_IRQENABLE_IPU1_OFFSET 0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DRA7XX_PRM_IRQSTATUS_DSP2_OFFSET 0x005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DRA7XX_PRM_IRQSTATUS_EVE1_OFFSET 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define DRA7XX_PRM_IRQSTATUS_EVE2_OFFSET 0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DRA7XX_PRM_IRQSTATUS_EVE3_OFFSET 0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DRA7XX_PRM_IRQSTATUS_EVE4_OFFSET 0x006c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DRA7XX_PRM_IRQSTATUS_IPU1_OFFSET 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DRA7XX_PRM_DEBUG_CFG1_OFFSET 0x00e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DRA7XX_PRM_DEBUG_CFG2_OFFSET 0x00e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DRA7XX_PRM_DEBUG_CFG3_OFFSET 0x00ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DRA7XX_PRM_DEBUG_OUT_OFFSET 0x00f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* PRM.CKGEN_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DRA7XX_CM_CLKSEL_SYSCLK1_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define DRA7XX_CM_CLKSEL_SYSCLK1 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define DRA7XX_CM_CLKSEL_WKUPAON_OFFSET 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DRA7XX_CM_CLKSEL_WKUPAON DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DRA7XX_CM_CLKSEL_ABE_PLL_REF_OFFSET 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DRA7XX_CM_CLKSEL_ABE_PLL_REF DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DRA7XX_CM_CLKSEL_SYS_OFFSET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DRA7XX_CM_CLKSEL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS_OFFSET 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DRA7XX_CM_CLKSEL_ABE_PLL_SYS_OFFSET 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DRA7XX_CM_CLKSEL_ABE_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define DRA7XX_CM_CLKSEL_ABE_24M_OFFSET 0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DRA7XX_CM_CLKSEL_ABE_24M DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x001c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DRA7XX_CM_CLKSEL_ABE_SYS_OFFSET 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DRA7XX_CM_CLKSEL_ABE_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DRA7XX_CM_CLKSEL_HDMI_TIMER_OFFSET 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define DRA7XX_CM_CLKSEL_HDMI_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DRA7XX_CM_CLKSEL_MCASP_SYS_OFFSET 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DRA7XX_CM_CLKSEL_MCASP_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x002c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DRA7XX_CM_CLKSEL_MLBP_MCASP_OFFSET 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define DRA7XX_CM_CLKSEL_MLBP_MCASP DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define DRA7XX_CM_CLKSEL_MLB_MCASP_OFFSET 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define DRA7XX_CM_CLKSEL_MLB_MCASP DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX_OFFSET 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define DRA7XX_CM_CLKSEL_SYS_CLK1_32K_OFFSET 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define DRA7XX_CM_CLKSEL_SYS_CLK1_32K DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define DRA7XX_CM_CLKSEL_TIMER_SYS_OFFSET 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define DRA7XX_CM_CLKSEL_TIMER_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX_OFFSET 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define DRA7XX_CM_CLKSEL_VIDEO1_TIMER_OFFSET 0x004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define DRA7XX_CM_CLKSEL_VIDEO1_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x004c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX_OFFSET 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define DRA7XX_CM_CLKSEL_VIDEO2_TIMER_OFFSET 0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define DRA7XX_CM_CLKSEL_VIDEO2_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define DRA7XX_CM_CLKSEL_CLKOUTMUX0_OFFSET 0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define DRA7XX_CM_CLKSEL_CLKOUTMUX0 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define DRA7XX_CM_CLKSEL_CLKOUTMUX1_OFFSET 0x005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define DRA7XX_CM_CLKSEL_CLKOUTMUX1 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x005c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define DRA7XX_CM_CLKSEL_CLKOUTMUX2_OFFSET 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define DRA7XX_CM_CLKSEL_CLKOUTMUX2 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define DRA7XX_CM_CLKSEL_HDMI_PLL_SYS_OFFSET 0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define DRA7XX_CM_CLKSEL_HDMI_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS_OFFSET 0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS_OFFSET 0x006c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x006c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define DRA7XX_CM_CLKSEL_ABE_CLK_DIV_OFFSET 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define DRA7XX_CM_CLKSEL_ABE_CLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define DRA7XX_CM_CLKSEL_ABE_GICLK_DIV_OFFSET 0x0074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define DRA7XX_CM_CLKSEL_ABE_GICLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define DRA7XX_CM_CLKSEL_AESS_FCLK_DIV_OFFSET 0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define DRA7XX_CM_CLKSEL_AESS_FCLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define DRA7XX_CM_CLKSEL_EVE_CLK_OFFSET 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define DRA7XX_CM_CLKSEL_EVE_CLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX_OFFSET 0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX_OFFSET 0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX_OFFSET 0x008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x008c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX_OFFSET 0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX_OFFSET 0x0094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX_OFFSET 0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX_OFFSET 0x009c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x009c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX_OFFSET 0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX_OFFSET 0x00a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX_OFFSET 0x00a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX_OFFSET 0x00ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00ac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX_OFFSET 0x00b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX_OFFSET 0x00b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX_OFFSET 0x00b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX_OFFSET 0x00bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00bc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX_OFFSET 0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX_OFFSET 0x00c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX_OFFSET 0x00c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX_OFFSET 0x00cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX_OFFSET 0x00d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX_OFFSET 0x00d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define DRA7XX_CM_CLKSEL_ABE_LP_CLK_OFFSET 0x00d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define DRA7XX_CM_CLKSEL_ABE_LP_CLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define DRA7XX_CM_CLKSEL_ADC_GFCLK_OFFSET 0x00dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define DRA7XX_CM_CLKSEL_ADC_GFCLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX_OFFSET 0x00e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00e0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* PRM.MPU_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define DRA7XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define DRA7XX_PM_MPU_PWRSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* PRM.DSP1_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define DRA7XX_PM_DSP1_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define DRA7XX_PM_DSP1_PWRSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define DRA7XX_RM_DSP1_RSTCTRL_OFFSET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define DRA7XX_RM_DSP1_RSTST_OFFSET 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* PRM.IPU_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define DRA7XX_PM_IPU_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define DRA7XX_PM_IPU_PWRSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define DRA7XX_RM_IPU1_RSTCTRL_OFFSET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define DRA7XX_RM_IPU1_RSTST_OFFSET 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define DRA7XX_PM_IPU_MCASP1_WKDEP_OFFSET 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET 0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define DRA7XX_PM_IPU_TIMER5_WKDEP_OFFSET 0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET 0x005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define DRA7XX_PM_IPU_TIMER6_WKDEP_OFFSET 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET 0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define DRA7XX_PM_IPU_TIMER7_WKDEP_OFFSET 0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET 0x006c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define DRA7XX_PM_IPU_TIMER8_WKDEP_OFFSET 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET 0x0074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define DRA7XX_PM_IPU_I2C5_WKDEP_OFFSET 0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET 0x007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define DRA7XX_PM_IPU_UART6_WKDEP_OFFSET 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET 0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* PRM.COREAON_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define DRA7XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define DRA7XX_PM_COREAON_SMARTREFLEX_CORE_WKDEP_OFFSET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define DRA7XX_PM_COREAON_SMARTREFLEX_GPU_WKDEP_OFFSET 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define DRA7XX_RM_COREAON_SMARTREFLEX_GPU_CONTEXT_OFFSET 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define DRA7XX_PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP_OFFSET 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define DRA7XX_RM_COREAON_SMARTREFLEX_DSPEVE_CONTEXT_OFFSET 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define DRA7XX_PM_COREAON_SMARTREFLEX_IVAHD_WKDEP_OFFSET 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define DRA7XX_RM_COREAON_SMARTREFLEX_IVAHD_CONTEXT_OFFSET 0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define DRA7XX_RM_COREAON_DUMMY_MODULE1_CONTEXT_OFFSET 0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define DRA7XX_RM_COREAON_DUMMY_MODULE2_CONTEXT_OFFSET 0x0094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define DRA7XX_RM_COREAON_DUMMY_MODULE3_CONTEXT_OFFSET 0x00a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define DRA7XX_RM_COREAON_DUMMY_MODULE4_CONTEXT_OFFSET 0x00b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* PRM.CORE_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define DRA7XX_PM_CORE_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define DRA7XX_PM_CORE_PWRSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define DRA7XX_RM_L3MAIN1_MMU_EDMA_CONTEXT_OFFSET 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define DRA7XX_PM_L3MAIN1_OCMC_RAM1_WKDEP_OFFSET 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define DRA7XX_RM_L3MAIN1_OCMC_RAM1_CONTEXT_OFFSET 0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define DRA7XX_PM_L3MAIN1_OCMC_RAM2_WKDEP_OFFSET 0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define DRA7XX_RM_L3MAIN1_OCMC_RAM2_CONTEXT_OFFSET 0x005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define DRA7XX_PM_L3MAIN1_OCMC_RAM3_WKDEP_OFFSET 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define DRA7XX_RM_L3MAIN1_OCMC_RAM3_CONTEXT_OFFSET 0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define DRA7XX_RM_L3MAIN1_OCMC_ROM_CONTEXT_OFFSET 0x006c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define DRA7XX_PM_L3MAIN1_TPCC_WKDEP_OFFSET 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET 0x0074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define DRA7XX_PM_L3MAIN1_TPTC1_WKDEP_OFFSET 0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET 0x007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define DRA7XX_PM_L3MAIN1_TPTC2_WKDEP_OFFSET 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET 0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET 0x008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET 0x0094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define DRA7XX_RM_L3MAIN1_SPARE_CME_CONTEXT_OFFSET 0x009c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define DRA7XX_RM_L3MAIN1_SPARE_HDMI_CONTEXT_OFFSET 0x00a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define DRA7XX_RM_L3MAIN1_SPARE_ICM_CONTEXT_OFFSET 0x00ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define DRA7XX_RM_L3MAIN1_SPARE_IVA2_CONTEXT_OFFSET 0x00b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define DRA7XX_RM_L3MAIN1_SPARE_SATA2_CONTEXT_OFFSET 0x00bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN4_CONTEXT_OFFSET 0x00c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN5_CONTEXT_OFFSET 0x00cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN6_CONTEXT_OFFSET 0x00d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL1_CONTEXT_OFFSET 0x00dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL2_CONTEXT_OFFSET 0x00f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL3_CONTEXT_OFFSET 0x00fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define DRA7XX_RM_IPU2_RSTCTRL_OFFSET 0x0210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define DRA7XX_RM_IPU2_RSTST_OFFSET 0x0214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET 0x0224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET 0x0324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET 0x0424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define DRA7XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET 0x042c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define DRA7XX_RM_EMIF_EMIF1_CONTEXT_OFFSET 0x0434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define DRA7XX_RM_EMIF_EMIF2_CONTEXT_OFFSET 0x043c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define DRA7XX_RM_EMIF_EMIF_DLL_CONTEXT_OFFSET 0x0444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET 0x0524
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET 0x062c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET 0x0634
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define DRA7XX_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define DRA7XX_RM_L4CFG_OCP2SCP2_CONTEXT_OFFSET 0x0644
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET 0x064c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET 0x0654
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET 0x065c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET 0x0664
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET 0x066c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET 0x0674
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET 0x067c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET 0x0684
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET 0x068c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET 0x0694
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET 0x069c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET 0x06a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_RTC_CONTEXT_OFFSET 0x06ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CONTEXT_OFFSET 0x06b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_WKUP_CONTEXT_OFFSET 0x06bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define DRA7XX_RM_L4CFG_IO_DELAY_BLOCK_CONTEXT_OFFSET 0x06c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET 0x0724
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define DRA7XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET 0x0744
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* PRM.IVA_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define DRA7XX_PM_IVA_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define DRA7XX_PM_IVA_PWRSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define DRA7XX_RM_IVA_RSTCTRL_OFFSET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define DRA7XX_RM_IVA_RSTST_OFFSET 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define DRA7XX_RM_IVA_IVA_CONTEXT_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define DRA7XX_RM_IVA_SL2_CONTEXT_OFFSET 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* PRM.CAM_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define DRA7XX_PM_CAM_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define DRA7XX_PM_CAM_PWRSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define DRA7XX_PM_CAM_VIP1_WKDEP_OFFSET 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define DRA7XX_RM_CAM_VIP1_CONTEXT_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define DRA7XX_PM_CAM_VIP2_WKDEP_OFFSET 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define DRA7XX_RM_CAM_VIP2_CONTEXT_OFFSET 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define DRA7XX_PM_CAM_VIP3_WKDEP_OFFSET 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define DRA7XX_RM_CAM_VIP3_CONTEXT_OFFSET 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define DRA7XX_RM_CAM_LVDSRX_CONTEXT_OFFSET 0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define DRA7XX_RM_CAM_CSI1_CONTEXT_OFFSET 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define DRA7XX_RM_CAM_CSI2_CONTEXT_OFFSET 0x004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* PRM.DSS_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define DRA7XX_PM_DSS_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define DRA7XX_PM_DSS_PWRSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define DRA7XX_PM_DSS_DSS_WKDEP_OFFSET 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define DRA7XX_PM_DSS_DSS2_WKDEP_OFFSET 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define DRA7XX_RM_DSS_SDVENC_CONTEXT_OFFSET 0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* PRM.GPU_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define DRA7XX_PM_GPU_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define DRA7XX_PM_GPU_PWRSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define DRA7XX_RM_GPU_GPU_CONTEXT_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* PRM.L3INIT_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define DRA7XX_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define DRA7XX_PM_L3INIT_PWRSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define DRA7XX_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define DRA7XX_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define DRA7XX_PM_L3INIT_USB_OTG_SS2_WKDEP_OFFSET 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define DRA7XX_PM_L3INIT_USB_OTG_SS3_WKDEP_OFFSET 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET 0x004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define DRA7XX_PM_L3INIT_USB_OTG_SS4_WKDEP_OFFSET 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET 0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define DRA7XX_RM_L3INIT_MLB_SS_CONTEXT_OFFSET 0x005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define DRA7XX_PM_L3INIT_PCIESS1_WKDEP_OFFSET 0x00b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET 0x00b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define DRA7XX_PM_L3INIT_PCIESS2_WKDEP_OFFSET 0x00b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET 0x00bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET 0x00d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET 0x00e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET 0x00ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define DRA7XX_PM_L3INIT_USB_OTG_SS1_WKDEP_OFFSET 0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET 0x00f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* PRM.L4PER_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define DRA7XX_PM_L4PER_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define DRA7XX_PM_L4PER_PWRSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define DRA7XX_RM_L4PER2_L4PER2_CONTEXT_OFFSET 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define DRA7XX_RM_L4PER3_L4PER3_CONTEXT_OFFSET 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define DRA7XX_RM_L4PER2_PRUSS1_CONTEXT_OFFSET 0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define DRA7XX_RM_L4PER2_PRUSS2_CONTEXT_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define DRA7XX_PM_L4PER_TIMER10_WKDEP_OFFSET 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define DRA7XX_PM_L4PER_TIMER11_WKDEP_OFFSET 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define DRA7XX_PM_L4PER_TIMER2_WKDEP_OFFSET 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET 0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define DRA7XX_PM_L4PER_TIMER3_WKDEP_OFFSET 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define DRA7XX_PM_L4PER_TIMER4_WKDEP_OFFSET 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET 0x004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define DRA7XX_PM_L4PER_TIMER9_WKDEP_OFFSET 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET 0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET 0x005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define DRA7XX_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define DRA7XX_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x006c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define DRA7XX_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define DRA7XX_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define DRA7XX_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET 0x0094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET 0x009c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define DRA7XX_PM_L4PER_I2C1_WKDEP_OFFSET 0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET 0x00a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define DRA7XX_PM_L4PER_I2C2_WKDEP_OFFSET 0x00a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET 0x00ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define DRA7XX_PM_L4PER_I2C3_WKDEP_OFFSET 0x00b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET 0x00b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define DRA7XX_PM_L4PER_I2C4_WKDEP_OFFSET 0x00b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET 0x00bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define DRA7XX_RM_L4PER_L4PER1_CONTEXT_OFFSET 0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET 0x00c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define DRA7XX_PM_L4PER_TIMER13_WKDEP_OFFSET 0x00c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET 0x00cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define DRA7XX_PM_L4PER_TIMER14_WKDEP_OFFSET 0x00d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET 0x00d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define DRA7XX_PM_L4PER_TIMER15_WKDEP_OFFSET 0x00d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET 0x00dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define DRA7XX_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x00f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define DRA7XX_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x00f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x00fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define DRA7XX_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define DRA7XX_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x010c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define DRA7XX_PM_L4PER_GPIO7_WKDEP_OFFSET 0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET 0x0114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define DRA7XX_PM_L4PER_GPIO8_WKDEP_OFFSET 0x0118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET 0x011c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define DRA7XX_PM_L4PER_MMC3_WKDEP_OFFSET 0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET 0x0124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define DRA7XX_PM_L4PER_MMC4_WKDEP_OFFSET 0x0128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET 0x012c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define DRA7XX_PM_L4PER_TIMER16_WKDEP_OFFSET 0x0130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET 0x0134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define DRA7XX_PM_L4PER2_QSPI_WKDEP_OFFSET 0x0138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET 0x013c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define DRA7XX_PM_L4PER_UART1_WKDEP_OFFSET 0x0140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET 0x0144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define DRA7XX_PM_L4PER_UART2_WKDEP_OFFSET 0x0148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET 0x014c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define DRA7XX_PM_L4PER_UART3_WKDEP_OFFSET 0x0150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET 0x0154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define DRA7XX_PM_L4PER_UART4_WKDEP_OFFSET 0x0158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET 0x015c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define DRA7XX_PM_L4PER2_MCASP2_WKDEP_OFFSET 0x0160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET 0x0164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define DRA7XX_PM_L4PER2_MCASP3_WKDEP_OFFSET 0x0168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET 0x016c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define DRA7XX_PM_L4PER_UART5_WKDEP_OFFSET 0x0170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET 0x0174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define DRA7XX_PM_L4PER2_MCASP5_WKDEP_OFFSET 0x0178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET 0x017c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define DRA7XX_PM_L4PER2_MCASP6_WKDEP_OFFSET 0x0180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET 0x0184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define DRA7XX_PM_L4PER2_MCASP7_WKDEP_OFFSET 0x0188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET 0x018c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define DRA7XX_PM_L4PER2_MCASP8_WKDEP_OFFSET 0x0190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET 0x0194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define DRA7XX_PM_L4PER2_MCASP4_WKDEP_OFFSET 0x0198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET 0x019c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET 0x01a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET 0x01ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x01b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define DRA7XX_RM_L4SEC_FPKA_CONTEXT_OFFSET 0x01bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET 0x01c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET 0x01cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define DRA7XX_PM_L4PER2_UART7_WKDEP_OFFSET 0x01d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET 0x01d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define DRA7XX_RM_L4SEC_DMA_CRYPTO_CONTEXT_OFFSET 0x01dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define DRA7XX_PM_L4PER2_UART8_WKDEP_OFFSET 0x01e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET 0x01e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define DRA7XX_PM_L4PER2_UART9_WKDEP_OFFSET 0x01e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET 0x01ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define DRA7XX_PM_L4PER2_DCAN2_WKDEP_OFFSET 0x01f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET 0x01f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define DRA7XX_RM_L4SEC_SHA2MD52_CONTEXT_OFFSET 0x01fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* PRM.CUSTEFUSE_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define DRA7XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define DRA7XX_PM_CUSTEFUSE_PWRSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define DRA7XX_RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* PRM.WKUPAON_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define DRA7XX_PM_WKUPAON_WD_TIMER1_WKDEP_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define DRA7XX_RM_WKUPAON_WD_TIMER1_CONTEXT_OFFSET 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define DRA7XX_PM_WKUPAON_WD_TIMER2_WKDEP_OFFSET 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define DRA7XX_PM_WKUPAON_GPIO1_WKDEP_OFFSET 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define DRA7XX_PM_WKUPAON_TIMER1_WKDEP_OFFSET 0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define DRA7XX_PM_WKUPAON_TIMER12_WKDEP_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define DRA7XX_RM_WKUPAON_SAR_RAM_CONTEXT_OFFSET 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define DRA7XX_PM_WKUPAON_KBD_WKDEP_OFFSET 0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define DRA7XX_RM_WKUPAON_KBD_CONTEXT_OFFSET 0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define DRA7XX_PM_WKUPAON_UART10_WKDEP_OFFSET 0x005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define DRA7XX_PM_WKUPAON_DCAN1_WKDEP_OFFSET 0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET 0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define DRA7XX_PM_WKUPAON_ADC_WKDEP_OFFSET 0x007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define DRA7XX_RM_WKUPAON_ADC_CONTEXT_OFFSET 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define DRA7XX_RM_WKUPAON_SPARE_SAFETY1_CONTEXT_OFFSET 0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define DRA7XX_RM_WKUPAON_SPARE_SAFETY2_CONTEXT_OFFSET 0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define DRA7XX_RM_WKUPAON_SPARE_SAFETY3_CONTEXT_OFFSET 0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define DRA7XX_RM_WKUPAON_SPARE_SAFETY4_CONTEXT_OFFSET 0x00a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define DRA7XX_RM_WKUPAON_SPARE_UNKNOWN2_CONTEXT_OFFSET 0x00b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define DRA7XX_RM_WKUPAON_SPARE_UNKNOWN3_CONTEXT_OFFSET 0x00b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* PRM.WKUPAON_CM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define DRA7XX_CM_WKUPAON_CLKSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define DRA7XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define DRA7XX_CM_WKUPAON_WD_TIMER1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define DRA7XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define DRA7XX_CM_WKUPAON_SAR_RAM_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define DRA7XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET 0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define DRA7XX_CM_WKUPAON_KBD_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define DRA7XX_CM_WKUPAON_UART10_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET 0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define DRA7XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET 0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define DRA7XX_CM_WKUPAON_SCRM_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define DRA7XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define DRA7XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define DRA7XX_CM_WKUPAON_ADC_CLKCTRL_OFFSET 0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define DRA7XX_CM_WKUPAON_ADC_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL_OFFSET 0x00b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL_OFFSET 0x00b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00b8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL_OFFSET 0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL_OFFSET 0x00c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00c8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL_OFFSET 0x00d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL_OFFSET 0x00d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00d8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* PRM.EMU_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define DRA7XX_PM_EMU_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define DRA7XX_PM_EMU_PWRSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define DRA7XX_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* PRM.EMU_CM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define DRA7XX_CM_EMU_CLKSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define DRA7XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define DRA7XX_CM_EMU_DEBUGSS_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_EMU_CM_INST, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define DRA7XX_CM_EMU_DYNAMICDEP_OFFSET 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define DRA7XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define DRA7XX_CM_EMU_MPU_EMU_DBG_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_EMU_CM_INST, 0x000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* PRM.DSP2_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define DRA7XX_PM_DSP2_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define DRA7XX_PM_DSP2_PWRSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define DRA7XX_RM_DSP2_RSTCTRL_OFFSET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define DRA7XX_RM_DSP2_RSTST_OFFSET 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* PRM.EVE1_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define DRA7XX_PM_EVE1_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define DRA7XX_PM_EVE1_PWRSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define DRA7XX_RM_EVE1_RSTCTRL_OFFSET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define DRA7XX_RM_EVE1_RSTST_OFFSET 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define DRA7XX_PM_EVE1_EVE1_WKDEP_OFFSET 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define DRA7XX_RM_EVE1_EVE1_CONTEXT_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* PRM.EVE2_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define DRA7XX_PM_EVE2_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define DRA7XX_PM_EVE2_PWRSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define DRA7XX_RM_EVE2_RSTCTRL_OFFSET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define DRA7XX_RM_EVE2_RSTST_OFFSET 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define DRA7XX_PM_EVE2_EVE2_WKDEP_OFFSET 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define DRA7XX_RM_EVE2_EVE2_CONTEXT_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /* PRM.EVE3_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define DRA7XX_PM_EVE3_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define DRA7XX_PM_EVE3_PWRSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define DRA7XX_RM_EVE3_RSTCTRL_OFFSET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define DRA7XX_RM_EVE3_RSTST_OFFSET 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define DRA7XX_PM_EVE3_EVE3_WKDEP_OFFSET 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define DRA7XX_RM_EVE3_EVE3_CONTEXT_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* PRM.EVE4_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define DRA7XX_PM_EVE4_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define DRA7XX_PM_EVE4_PWRSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define DRA7XX_RM_EVE4_RSTCTRL_OFFSET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define DRA7XX_RM_EVE4_RSTST_OFFSET 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define DRA7XX_PM_EVE4_EVE4_WKDEP_OFFSET 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define DRA7XX_RM_EVE4_EVE4_CONTEXT_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* PRM.RTC_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define DRA7XX_PM_RTC_RTCSS_WKDEP_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /* PRM.VPE_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define DRA7XX_PM_VPE_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define DRA7XX_PM_VPE_PWRSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define DRA7XX_PM_VPE_VPE_WKDEP_OFFSET 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define DRA7XX_RM_VPE_VPE_CONTEXT_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* PRM.DEVICE_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define DRA7XX_PRM_RSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define DRA7XX_PRM_RSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define DRA7XX_PRM_RSTTIME_OFFSET 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define DRA7XX_PRM_CLKREQCTRL_OFFSET 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define DRA7XX_PRM_VOLTCTRL_OFFSET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define DRA7XX_PRM_PWRREQCTRL_OFFSET 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define DRA7XX_PRM_PSCON_COUNT_OFFSET 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define DRA7XX_PRM_IO_COUNT_OFFSET 0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define DRA7XX_PRM_IO_PMCTRL_OFFSET 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define DRA7XX_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define DRA7XX_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define DRA7XX_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define DRA7XX_PRM_VOLTSETUP_MM_OFF_OFFSET 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define DRA7XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define DRA7XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define DRA7XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET 0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define DRA7XX_PRM_SRAM_COUNT_OFFSET 0x00bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define DRA7XX_PRM_SRAM_WKUP_SETUP_OFFSET 0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define DRA7XX_PRM_SLDO_CORE_SETUP_OFFSET 0x00c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define DRA7XX_PRM_SLDO_CORE_CTRL_OFFSET 0x00c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define DRA7XX_PRM_SLDO_MPU_SETUP_OFFSET 0x00cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define DRA7XX_PRM_SLDO_MPU_CTRL_OFFSET 0x00d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define DRA7XX_PRM_SLDO_GPU_SETUP_OFFSET 0x00d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define DRA7XX_PRM_SLDO_GPU_CTRL_OFFSET 0x00d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define DRA7XX_PRM_ABBLDO_MPU_SETUP_OFFSET 0x00dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define DRA7XX_PRM_ABBLDO_MPU_CTRL_OFFSET 0x00e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define DRA7XX_PRM_ABBLDO_GPU_SETUP_OFFSET 0x00e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define DRA7XX_PRM_ABBLDO_GPU_CTRL_OFFSET 0x00e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define DRA7XX_PRM_BANDGAP_SETUP_OFFSET 0x00ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define DRA7XX_PRM_DEVICE_OFF_CTRL_OFFSET 0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define DRA7XX_PRM_PHASE1_CNDP_OFFSET 0x00f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define DRA7XX_PRM_PHASE2A_CNDP_OFFSET 0x00f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define DRA7XX_PRM_PHASE2B_CNDP_OFFSET 0x00fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define DRA7XX_PRM_MODEM_IF_CTRL_OFFSET 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define DRA7XX_PRM_VOLTST_MPU_OFFSET 0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define DRA7XX_PRM_VOLTST_MM_OFFSET 0x0114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define DRA7XX_PRM_SLDO_DSPEVE_SETUP_OFFSET 0x0118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define DRA7XX_PRM_SLDO_IVA_SETUP_OFFSET 0x011c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define DRA7XX_PRM_ABBLDO_DSPEVE_CTRL_OFFSET 0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define DRA7XX_PRM_ABBLDO_IVA_CTRL_OFFSET 0x0124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define DRA7XX_PRM_SLDO_DSPEVE_CTRL_OFFSET 0x0128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define DRA7XX_PRM_SLDO_IVA_CTRL_OFFSET 0x012c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define DRA7XX_PRM_ABBLDO_DSPEVE_SETUP_OFFSET 0x0130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define DRA7XX_PRM_ABBLDO_IVA_SETUP_OFFSET 0x0134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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