^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP54xx PRM instance offset macros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Paul Walmsley (paul@pwsan.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Rajendra Nayak (rnayak@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Benoit Cousson (b-cousson@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This file is automatically generated from the OMAP hardware databases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * We respectfully ask that any modifications to this file be coordinated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * with the public linux-omap@vger.kernel.org mailing list and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * authors above to ensure that the autogeneration scripts are kept
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * up-to-date with the file contents.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #ifndef __ARCH_ARM_MACH_OMAP2_PRM54XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define __ARCH_ARM_MACH_OMAP2_PRM54XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "prm44xx_54xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "prm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define OMAP54XX_PRM_BASE 0x4ae06000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define OMAP54XX_PRM_REGADDR(inst, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE + (inst) + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* PRM instances */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OMAP54XX_PRM_OCP_SOCKET_INST 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OMAP54XX_PRM_CKGEN_INST 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OMAP54XX_PRM_MPU_INST 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OMAP54XX_PRM_DSP_INST 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OMAP54XX_PRM_ABE_INST 0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OMAP54XX_PRM_COREAON_INST 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OMAP54XX_PRM_CORE_INST 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OMAP54XX_PRM_IVA_INST 0x1200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OMAP54XX_PRM_CAM_INST 0x1300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define OMAP54XX_PRM_DSS_INST 0x1400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OMAP54XX_PRM_GPU_INST 0x1500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OMAP54XX_PRM_L3INIT_INST 0x1600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OMAP54XX_PRM_CUSTEFUSE_INST 0x1700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OMAP54XX_PRM_WKUPAON_INST 0x1800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OMAP54XX_PRM_WKUPAON_CM_INST 0x1900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OMAP54XX_PRM_EMU_INST 0x1a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OMAP54XX_PRM_EMU_CM_INST 0x1b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OMAP54XX_PRM_DEVICE_INST 0x1c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OMAP54XX_PRM_INSTR_INST 0x1f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* PRM clockdomain register offsets (from instance start) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OMAP54XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OMAP54XX_PRM_EMU_CM_EMU_CDOFFS 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* PRM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* PRM.OCP_SOCKET_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OMAP54XX_REVISION_PRM_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OMAP54XX_PRM_IRQSTATUS_MPU_OFFSET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OMAP54XX_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OMAP54XX_PRM_IRQENABLE_MPU_OFFSET 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OMAP54XX_PRM_IRQENABLE_MPU_2_OFFSET 0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OMAP54XX_PRM_IRQSTATUS_IPU_OFFSET 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OMAP54XX_PRM_IRQENABLE_IPU_OFFSET 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OMAP54XX_PRM_IRQSTATUS_DSP_OFFSET 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OMAP54XX_PRM_IRQENABLE_DSP_OFFSET 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OMAP54XX_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OMAP54XX_CM_PRM_PROFILING_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_OCP_SOCKET_INST, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OMAP54XX_PRM_DEBUG_OUT_OFFSET 0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OMAP54XX_PRM_DEBUG_TRANS_CFG_OFFSET 0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OMAP54XX_PRM_DEBUG_OFF_TRANS_OFFSET 0x0094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OMAP54XX_PRM_DEBUG_CORE_RET_TRANS_OFFSET 0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OMAP54XX_PRM_DEBUG_MPU_RET_TRANS_OFFSET 0x009c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OMAP54XX_PRM_DEBUG_MM_RET_TRANS_OFFSET 0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OMAP54XX_PRM_DEBUG_WKUPAON_FD_TRANS_OFFSET 0x00a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* PRM.CKGEN_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OMAP54XX_CM_CLKSEL_ABE_DSS_SYS_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OMAP54XX_CM_CLKSEL_ABE_DSS_SYS OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OMAP54XX_CM_CLKSEL_WKUPAON_OFFSET 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OMAP54XX_CM_CLKSEL_WKUPAON OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OMAP54XX_CM_CLKSEL_ABE_PLL_REF_OFFSET 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OMAP54XX_CM_CLKSEL_ABE_PLL_REF OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OMAP54XX_CM_CLKSEL_SYS_OFFSET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OMAP54XX_CM_CLKSEL_SYS OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* PRM.MPU_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define OMAP54XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define OMAP54XX_PM_MPU_PWRSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* PRM.DSP_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define OMAP54XX_PM_DSP_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define OMAP54XX_PM_DSP_PWRSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define OMAP54XX_RM_DSP_RSTCTRL_OFFSET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define OMAP54XX_RM_DSP_RSTST_OFFSET 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* PRM.ABE_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define OMAP54XX_PM_ABE_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define OMAP54XX_PM_ABE_PWRSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define OMAP54XX_RM_ABE_AESS_CONTEXT_OFFSET 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define OMAP54XX_PM_ABE_MCPDM_WKDEP_OFFSET 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define OMAP54XX_PM_ABE_DMIC_WKDEP_OFFSET 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET 0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define OMAP54XX_PM_ABE_MCASP_WKDEP_OFFSET 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define OMAP54XX_RM_ABE_MCASP_CONTEXT_OFFSET 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define OMAP54XX_PM_ABE_MCBSP1_WKDEP_OFFSET 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET 0x004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define OMAP54XX_PM_ABE_MCBSP2_WKDEP_OFFSET 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET 0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define OMAP54XX_PM_ABE_MCBSP3_WKDEP_OFFSET 0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET 0x005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define OMAP54XX_PM_ABE_SLIMBUS1_WKDEP_OFFSET 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define OMAP54XX_RM_ABE_SLIMBUS1_CONTEXT_OFFSET 0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define OMAP54XX_PM_ABE_TIMER5_WKDEP_OFFSET 0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET 0x006c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define OMAP54XX_PM_ABE_TIMER6_WKDEP_OFFSET 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET 0x0074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define OMAP54XX_PM_ABE_TIMER7_WKDEP_OFFSET 0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET 0x007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define OMAP54XX_PM_ABE_TIMER8_WKDEP_OFFSET 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET 0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define OMAP54XX_PM_ABE_WD_TIMER3_WKDEP_OFFSET 0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define OMAP54XX_RM_ABE_WD_TIMER3_CONTEXT_OFFSET 0x008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* PRM.COREAON_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define OMAP54XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define OMAP54XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define OMAP54XX_PM_COREAON_SMARTREFLEX_MM_WKDEP_OFFSET 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define OMAP54XX_RM_COREAON_SMARTREFLEX_MM_CONTEXT_OFFSET 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define OMAP54XX_PM_COREAON_SMARTREFLEX_CORE_WKDEP_OFFSET 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define OMAP54XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET 0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* PRM.CORE_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define OMAP54XX_PM_CORE_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define OMAP54XX_PM_CORE_PWRSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET 0x0124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define OMAP54XX_RM_L3MAIN2_GPMC_CONTEXT_OFFSET 0x012c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define OMAP54XX_RM_L3MAIN2_OCMC_RAM_CONTEXT_OFFSET 0x0134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define OMAP54XX_RM_IPU_RSTCTRL_OFFSET 0x0210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define OMAP54XX_RM_IPU_RSTST_OFFSET 0x0214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET 0x0224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET 0x0324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET 0x0424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define OMAP54XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET 0x042c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET 0x0434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET 0x043c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define OMAP54XX_RM_EMIF_EMIF_DLL_CONTEXT_OFFSET 0x0444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define OMAP54XX_RM_C2C_C2C_CONTEXT_OFFSET 0x0524
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define OMAP54XX_RM_C2C_MODEM_ICR_CONTEXT_OFFSET 0x052c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define OMAP54XX_RM_C2C_C2C_OCP_FW_CONTEXT_OFFSET 0x0534
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET 0x062c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET 0x0634
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define OMAP54XX_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define OMAP54XX_RM_L4CFG_OCP2SCP2_CONTEXT_OFFSET 0x0644
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET 0x0724
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define OMAP54XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET 0x0744
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define OMAP54XX_RM_MIPIEXT_LLI_CONTEXT_OFFSET 0x0824
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define OMAP54XX_RM_MIPIEXT_LLI_OCP_FW_CONTEXT_OFFSET 0x082c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define OMAP54XX_RM_MIPIEXT_MPHY_CONTEXT_OFFSET 0x0834
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define OMAP54XX_PM_L4PER_TIMER10_WKDEP_OFFSET 0x0928
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET 0x092c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define OMAP54XX_PM_L4PER_TIMER11_WKDEP_OFFSET 0x0930
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET 0x0934
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define OMAP54XX_PM_L4PER_TIMER2_WKDEP_OFFSET 0x0938
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET 0x093c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define OMAP54XX_PM_L4PER_TIMER3_WKDEP_OFFSET 0x0940
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET 0x0944
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define OMAP54XX_PM_L4PER_TIMER4_WKDEP_OFFSET 0x0948
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET 0x094c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define OMAP54XX_PM_L4PER_TIMER9_WKDEP_OFFSET 0x0950
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET 0x0954
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define OMAP54XX_RM_L4PER_ELM_CONTEXT_OFFSET 0x095c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define OMAP54XX_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0960
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0964
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define OMAP54XX_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0968
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x096c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define OMAP54XX_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0970
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0974
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define OMAP54XX_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0978
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x097c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define OMAP54XX_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0980
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0984
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define OMAP54XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x098c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define OMAP54XX_PM_L4PER_I2C1_WKDEP_OFFSET 0x09a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET 0x09a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define OMAP54XX_PM_L4PER_I2C2_WKDEP_OFFSET 0x09a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET 0x09ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define OMAP54XX_PM_L4PER_I2C3_WKDEP_OFFSET 0x09b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET 0x09b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define OMAP54XX_PM_L4PER_I2C4_WKDEP_OFFSET 0x09b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET 0x09bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET 0x09c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define OMAP54XX_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x09f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x09f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define OMAP54XX_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x09f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x09fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define OMAP54XX_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0a04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define OMAP54XX_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0a08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x0a0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define OMAP54XX_PM_L4PER_GPIO7_WKDEP_OFFSET 0x0a10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET 0x0a14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define OMAP54XX_PM_L4PER_GPIO8_WKDEP_OFFSET 0x0a18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET 0x0a1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define OMAP54XX_PM_L4PER_MMC3_WKDEP_OFFSET 0x0a20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET 0x0a24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define OMAP54XX_PM_L4PER_MMC4_WKDEP_OFFSET 0x0a28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET 0x0a2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define OMAP54XX_PM_L4PER_UART1_WKDEP_OFFSET 0x0a40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET 0x0a44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define OMAP54XX_PM_L4PER_UART2_WKDEP_OFFSET 0x0a48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET 0x0a4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define OMAP54XX_PM_L4PER_UART3_WKDEP_OFFSET 0x0a50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET 0x0a54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET 0x0a58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define OMAP54XX_PM_L4PER_UART4_WKDEP_OFFSET 0x0a5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define OMAP54XX_PM_L4PER_MMC5_WKDEP_OFFSET 0x0a60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET 0x0a64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define OMAP54XX_PM_L4PER_I2C5_WKDEP_OFFSET 0x0a68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET 0x0a6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define OMAP54XX_PM_L4PER_UART5_WKDEP_OFFSET 0x0a70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET 0x0a74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define OMAP54XX_PM_L4PER_UART6_WKDEP_OFFSET 0x0a78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET 0x0a7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define OMAP54XX_RM_L4SEC_AES1_CONTEXT_OFFSET 0x0aa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define OMAP54XX_RM_L4SEC_AES2_CONTEXT_OFFSET 0x0aac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define OMAP54XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x0ab4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define OMAP54XX_RM_L4SEC_FPKA_CONTEXT_OFFSET 0x0abc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define OMAP54XX_RM_L4SEC_RNG_CONTEXT_OFFSET 0x0ac4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define OMAP54XX_RM_L4SEC_SHA2MD5_CONTEXT_OFFSET 0x0acc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define OMAP54XX_RM_L4SEC_DMA_CRYPTO_CONTEXT_OFFSET 0x0adc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* PRM.IVA_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define OMAP54XX_PM_IVA_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define OMAP54XX_PM_IVA_PWRSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define OMAP54XX_RM_IVA_RSTCTRL_OFFSET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define OMAP54XX_RM_IVA_RSTST_OFFSET 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define OMAP54XX_RM_IVA_IVA_CONTEXT_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define OMAP54XX_RM_IVA_SL2_CONTEXT_OFFSET 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* PRM.CAM_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define OMAP54XX_PM_CAM_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define OMAP54XX_PM_CAM_PWRSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define OMAP54XX_RM_CAM_ISS_CONTEXT_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define OMAP54XX_RM_CAM_FDIF_CONTEXT_OFFSET 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define OMAP54XX_RM_CAM_CAL_CONTEXT_OFFSET 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* PRM.DSS_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define OMAP54XX_PM_DSS_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define OMAP54XX_PM_DSS_PWRSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define OMAP54XX_PM_DSS_DSS_WKDEP_OFFSET 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define OMAP54XX_RM_DSS_BB2D_CONTEXT_OFFSET 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* PRM.GPU_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define OMAP54XX_PM_GPU_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define OMAP54XX_PM_GPU_PWRSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define OMAP54XX_RM_GPU_GPU_CONTEXT_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* PRM.L3INIT_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define OMAP54XX_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define OMAP54XX_PM_L3INIT_PWRSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define OMAP54XX_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define OMAP54XX_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define OMAP54XX_PM_L3INIT_HSI_WKDEP_OFFSET 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define OMAP54XX_RM_L3INIT_HSI_CONTEXT_OFFSET 0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define OMAP54XX_PM_L3INIT_UNIPRO2_WKDEP_OFFSET 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define OMAP54XX_RM_L3INIT_UNIPRO2_CONTEXT_OFFSET 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define OMAP54XX_PM_L3INIT_USB_HOST_HS_WKDEP_OFFSET 0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET 0x005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define OMAP54XX_PM_L3INIT_USB_TLL_HS_WKDEP_OFFSET 0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET 0x006c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define OMAP54XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define OMAP54XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET 0x00e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET 0x00ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define OMAP54XX_PM_L3INIT_USB_OTG_SS_WKDEP_OFFSET 0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET 0x00f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* PRM.CUSTEFUSE_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define OMAP54XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define OMAP54XX_PM_CUSTEFUSE_PWRSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define OMAP54XX_RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* PRM.WKUPAON_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define OMAP54XX_RM_WKUPAON_WD_TIMER1_CONTEXT_OFFSET 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define OMAP54XX_PM_WKUPAON_WD_TIMER2_WKDEP_OFFSET 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define OMAP54XX_PM_WKUPAON_GPIO1_WKDEP_OFFSET 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET 0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define OMAP54XX_PM_WKUPAON_TIMER1_WKDEP_OFFSET 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define OMAP54XX_PM_WKUPAON_TIMER12_WKDEP_OFFSET 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define OMAP54XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET 0x004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET 0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define OMAP54XX_RM_WKUPAON_SAR_RAM_CONTEXT_OFFSET 0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define OMAP54XX_PM_WKUPAON_KBD_WKDEP_OFFSET 0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET 0x007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* PRM.WKUPAON_CM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define OMAP54XX_CM_WKUPAON_CLKSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET 0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define OMAP54XX_CM_WKUPAON_KBD_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET 0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* PRM.EMU_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define OMAP54XX_PM_EMU_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define OMAP54XX_PM_EMU_PWRSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define OMAP54XX_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* PRM.EMU_CM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define OMAP54XX_CM_EMU_CLKSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define OMAP54XX_CM_EMU_DYNAMICDEP_OFFSET 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_EMU_CM_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_EMU_CM_INST, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* PRM.DEVICE_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define OMAP54XX_PRM_RSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define OMAP54XX_PRM_RSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define OMAP54XX_PRM_RSTTIME_OFFSET 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define OMAP54XX_PRM_CLKREQCTRL_OFFSET 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define OMAP54XX_PRM_VOLTCTRL_OFFSET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define OMAP54XX_PRM_PWRREQCTRL_OFFSET 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define OMAP54XX_PRM_PSCON_COUNT_OFFSET 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define OMAP54XX_PRM_IO_COUNT_OFFSET 0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define OMAP54XX_PRM_IO_PMCTRL_OFFSET 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define OMAP54XX_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define OMAP54XX_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define OMAP54XX_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define OMAP54XX_PRM_VOLTSETUP_MM_OFF_OFFSET 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define OMAP54XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define OMAP54XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define OMAP54XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET 0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define OMAP54XX_PRM_VP_CORE_CONFIG_OFFSET 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define OMAP54XX_PRM_VP_CORE_STATUS_OFFSET 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define OMAP54XX_PRM_VP_CORE_VLIMITTO_OFFSET 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define OMAP54XX_PRM_VP_CORE_VOLTAGE_OFFSET 0x004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define OMAP54XX_PRM_VP_CORE_VSTEPMAX_OFFSET 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define OMAP54XX_PRM_VP_CORE_VSTEPMIN_OFFSET 0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define OMAP54XX_PRM_VP_MPU_CONFIG_OFFSET 0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define OMAP54XX_PRM_VP_MPU_STATUS_OFFSET 0x005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define OMAP54XX_PRM_VP_MPU_VLIMITTO_OFFSET 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define OMAP54XX_PRM_VP_MPU_VOLTAGE_OFFSET 0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define OMAP54XX_PRM_VP_MPU_VSTEPMAX_OFFSET 0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define OMAP54XX_PRM_VP_MPU_VSTEPMIN_OFFSET 0x006c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define OMAP54XX_PRM_VP_MM_CONFIG_OFFSET 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define OMAP54XX_PRM_VP_MM_STATUS_OFFSET 0x0074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define OMAP54XX_PRM_VP_MM_VLIMITTO_OFFSET 0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define OMAP54XX_PRM_VP_MM_VOLTAGE_OFFSET 0x007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define OMAP54XX_PRM_VP_MM_VSTEPMAX_OFFSET 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define OMAP54XX_PRM_VP_MM_VSTEPMIN_OFFSET 0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define OMAP54XX_PRM_VC_SMPS_CORE_CONFIG_OFFSET 0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define OMAP54XX_PRM_VC_SMPS_MM_CONFIG_OFFSET 0x008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define OMAP54XX_PRM_VC_SMPS_MPU_CONFIG_OFFSET 0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define OMAP54XX_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET 0x0094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define OMAP54XX_PRM_VC_VAL_CMD_VDD_MM_L_OFFSET 0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define OMAP54XX_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET 0x009c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define OMAP54XX_PRM_VC_VAL_BYPASS_OFFSET 0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define OMAP54XX_PRM_VC_CORE_ERRST_OFFSET 0x00a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define OMAP54XX_PRM_VC_MM_ERRST_OFFSET 0x00a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define OMAP54XX_PRM_VC_MPU_ERRST_OFFSET 0x00ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define OMAP54XX_PRM_VC_BYPASS_ERRST_OFFSET 0x00b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define OMAP54XX_PRM_VC_CFG_I2C_MODE_OFFSET 0x00b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define OMAP54XX_PRM_VC_CFG_I2C_CLK_OFFSET 0x00b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define OMAP54XX_PRM_SRAM_COUNT_OFFSET 0x00bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define OMAP54XX_PRM_SRAM_WKUP_SETUP_OFFSET 0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define OMAP54XX_PRM_SLDO_CORE_SETUP_OFFSET 0x00c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define OMAP54XX_PRM_SLDO_CORE_CTRL_OFFSET 0x00c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define OMAP54XX_PRM_SLDO_MPU_SETUP_OFFSET 0x00cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define OMAP54XX_PRM_SLDO_MPU_CTRL_OFFSET 0x00d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define OMAP54XX_PRM_SLDO_MM_SETUP_OFFSET 0x00d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define OMAP54XX_PRM_SLDO_MM_CTRL_OFFSET 0x00d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define OMAP54XX_PRM_ABBLDO_MPU_SETUP_OFFSET 0x00dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define OMAP54XX_PRM_ABBLDO_MPU_CTRL_OFFSET 0x00e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define OMAP54XX_PRM_ABBLDO_MM_SETUP_OFFSET 0x00e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define OMAP54XX_PRM_ABBLDO_MM_CTRL_OFFSET 0x00e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define OMAP54XX_PRM_BANDGAP_SETUP_OFFSET 0x00ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define OMAP54XX_PRM_DEVICE_OFF_CTRL_OFFSET 0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define OMAP54XX_PRM_PHASE1_CNDP_OFFSET 0x00f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define OMAP54XX_PRM_PHASE2A_CNDP_OFFSET 0x00f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define OMAP54XX_PRM_PHASE2B_CNDP_OFFSET 0x00fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define OMAP54XX_PRM_MODEM_IF_CTRL_OFFSET 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define OMAP54XX_PRM_VOLTST_MPU_OFFSET 0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define OMAP54XX_PRM_VOLTST_MM_OFFSET 0x0114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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