Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * OMAP44xx PRM instance offset macros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2009-2011 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2009-2010 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Paul Walmsley (paul@pwsan.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Rajendra Nayak (rnayak@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Benoit Cousson (b-cousson@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * This file is automatically generated from the OMAP hardware databases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * We respectfully ask that any modifications to this file be coordinated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * with the public linux-omap@vger.kernel.org mailing list and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * authors above to ensure that the autogeneration scripts are kept
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * up-to-date with the file contents.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *     or "OMAP4430".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define __ARCH_ARM_MACH_OMAP2_PRM44XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include "prm44xx_54xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include "prm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define OMAP4430_PRM_BASE		0x4a306000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define OMAP44XX_PRM_REGADDR(inst, reg)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) /* PRM instances */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define OMAP4430_PRM_OCP_SOCKET_INST	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define OMAP4430_PRM_CKGEN_INST		0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define OMAP4430_PRM_MPU_INST		0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define OMAP4430_PRM_TESLA_INST		0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define OMAP4430_PRM_ABE_INST		0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define OMAP4430_PRM_ALWAYS_ON_INST	0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define OMAP4430_PRM_CORE_INST		0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define OMAP4430_PRM_IVAHD_INST		0x0f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define OMAP4430_PRM_CAM_INST		0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define OMAP4430_PRM_DSS_INST		0x1100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define OMAP4430_PRM_GFX_INST		0x1200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define OMAP4430_PRM_L3INIT_INST	0x1300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define OMAP4430_PRM_L4PER_INST		0x1400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define OMAP4430_PRM_CEFUSE_INST	0x1600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define OMAP4430_PRM_WKUP_INST		0x1700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define OMAP4430_PRM_WKUP_CM_INST	0x1800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define OMAP4430_PRM_EMU_INST		0x1900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define OMAP4430_PRM_EMU_CM_INST	0x1a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define OMAP4430_PRM_DEVICE_INST	0x1b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define OMAP4430_PRM_INSTR_INST		0x1f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) /* PRM clockdomain register offsets (from instance start) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define OMAP4430_PRM_EMU_CM_EMU_CDOFFS		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) /* OMAP4 specific register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define OMAP4_RM_RSTCTRL				0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define OMAP4_RM_RSTST					0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define OMAP4_RM_RSTTIME				0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define OMAP4_PM_PWSTCTRL				0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define OMAP4_PM_PWSTST					0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) /* PRM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) /* PRM.OCP_SOCKET_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define OMAP4_REVISION_PRM_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define OMAP4430_REVISION_PRM				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define OMAP4_PRM_IRQSTATUS_MPU_OFFSET			0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define OMAP4430_PRM_IRQSTATUS_MPU			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET		0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define OMAP4430_PRM_IRQSTATUS_MPU_2			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define OMAP4_PRM_IRQENABLE_MPU_OFFSET			0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define OMAP4430_PRM_IRQENABLE_MPU			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define OMAP4_PRM_IRQENABLE_MPU_2_OFFSET		0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define OMAP4430_PRM_IRQENABLE_MPU_2			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x001c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define OMAP4_PRM_IRQSTATUS_DUCATI_OFFSET		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define OMAP4430_PRM_IRQSTATUS_DUCATI			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define OMAP4_PRM_IRQENABLE_DUCATI_OFFSET		0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define OMAP4430_PRM_IRQENABLE_DUCATI			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define OMAP4_PRM_IRQSTATUS_TESLA_OFFSET		0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define OMAP4430_PRM_IRQSTATUS_TESLA			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define OMAP4_PRM_IRQENABLE_TESLA_OFFSET		0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define OMAP4430_PRM_IRQENABLE_TESLA			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define OMAP4_CM_PRM_PROFILING_CLKCTRL_OFFSET		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define OMAP4430_CM_PRM_PROFILING_CLKCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) /* PRM.CKGEN_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define OMAP4430_CM_ABE_DSS_SYS_CLKSEL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET			0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define OMAP4430_CM_L4_WKUP_CLKSEL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET		0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define OMAP4430_CM_ABE_PLL_REF_CLKSEL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define OMAP4_CM_SYS_CLKSEL_OFFSET			0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define OMAP4430_CM_SYS_CLKSEL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* PRM.MPU_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define OMAP4_PM_MPU_PWRSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define OMAP4430_PM_MPU_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define OMAP4_PM_MPU_PWRSTST_OFFSET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define OMAP4430_PM_MPU_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define OMAP4_RM_MPU_RSTST_OFFSET			0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define OMAP4430_RM_MPU_RSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define OMAP4_RM_MPU_MPU_CONTEXT_OFFSET			0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define OMAP4430_RM_MPU_MPU_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* PRM.TESLA_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define OMAP4_PM_TESLA_PWRSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define OMAP4430_PM_TESLA_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define OMAP4_PM_TESLA_PWRSTST_OFFSET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define OMAP4430_PM_TESLA_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define OMAP4_RM_TESLA_RSTCTRL_OFFSET			0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define OMAP4430_RM_TESLA_RSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define OMAP4_RM_TESLA_RSTST_OFFSET			0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define OMAP4430_RM_TESLA_RSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET		0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define OMAP4430_RM_TESLA_TESLA_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* PRM.ABE_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define OMAP4_PM_ABE_PWRSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define OMAP4430_PM_ABE_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define OMAP4_PM_ABE_PWRSTST_OFFSET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define OMAP4430_PM_ABE_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define OMAP4_RM_ABE_AESS_CONTEXT_OFFSET		0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define OMAP4430_RM_ABE_AESS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x002c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define OMAP4_PM_ABE_PDM_WKDEP_OFFSET			0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define OMAP4430_PM_ABE_PDM_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define OMAP4_RM_ABE_PDM_CONTEXT_OFFSET			0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define OMAP4430_RM_ABE_PDM_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define OMAP4_PM_ABE_DMIC_WKDEP_OFFSET			0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define OMAP4430_PM_ABE_DMIC_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET		0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define OMAP4430_RM_ABE_DMIC_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x003c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define OMAP4_PM_ABE_MCASP_WKDEP_OFFSET			0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define OMAP4430_PM_ABE_MCASP_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET		0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define OMAP4430_RM_ABE_MCASP_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define OMAP4_PM_ABE_MCBSP1_WKDEP_OFFSET		0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define OMAP4430_PM_ABE_MCBSP1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET		0x004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define OMAP4430_RM_ABE_MCBSP1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x004c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define OMAP4_PM_ABE_MCBSP2_WKDEP_OFFSET		0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define OMAP4430_PM_ABE_MCBSP2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET		0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define OMAP4430_RM_ABE_MCBSP2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define OMAP4_PM_ABE_MCBSP3_WKDEP_OFFSET		0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define OMAP4430_PM_ABE_MCBSP3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET		0x005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define OMAP4430_RM_ABE_MCBSP3_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x005c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define OMAP4_PM_ABE_SLIMBUS_WKDEP_OFFSET		0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define OMAP4430_PM_ABE_SLIMBUS_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET		0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define OMAP4430_RM_ABE_SLIMBUS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define OMAP4_PM_ABE_TIMER5_WKDEP_OFFSET		0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define OMAP4430_PM_ABE_TIMER5_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET		0x006c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define OMAP4430_RM_ABE_TIMER5_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x006c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define OMAP4_PM_ABE_TIMER6_WKDEP_OFFSET		0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define OMAP4430_PM_ABE_TIMER6_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET		0x0074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define OMAP4430_RM_ABE_TIMER6_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define OMAP4_PM_ABE_TIMER7_WKDEP_OFFSET		0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define OMAP4430_PM_ABE_TIMER7_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET		0x007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define OMAP4430_RM_ABE_TIMER7_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x007c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define OMAP4_PM_ABE_TIMER8_WKDEP_OFFSET		0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define OMAP4430_PM_ABE_TIMER8_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET		0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define OMAP4430_RM_ABE_TIMER8_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define OMAP4_PM_ABE_WDT3_WKDEP_OFFSET			0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define OMAP4430_PM_ABE_WDT3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET		0x008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define OMAP4430_RM_ABE_WDT3_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x008c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* PRM.ALWAYS_ON_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define OMAP4_RM_ALWON_MDMINTC_CONTEXT_OFFSET		0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define OMAP4430_RM_ALWON_MDMINTC_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define OMAP4_PM_ALWON_SR_MPU_WKDEP_OFFSET		0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define OMAP4430_PM_ALWON_SR_MPU_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET		0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define OMAP4430_RM_ALWON_SR_MPU_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x002c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define OMAP4_PM_ALWON_SR_IVA_WKDEP_OFFSET		0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define OMAP4430_PM_ALWON_SR_IVA_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET		0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define OMAP4430_RM_ALWON_SR_IVA_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define OMAP4_PM_ALWON_SR_CORE_WKDEP_OFFSET		0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define OMAP4430_PM_ALWON_SR_CORE_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET		0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define OMAP4430_RM_ALWON_SR_CORE_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x003c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* PRM.CORE_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define OMAP4_PM_CORE_PWRSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define OMAP4430_PM_CORE_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define OMAP4_PM_CORE_PWRSTST_OFFSET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define OMAP4430_PM_CORE_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET		0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define OMAP4430_RM_L3_1_L3_1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET		0x0124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define OMAP4430_RM_L3_2_L3_2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET		0x012c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define OMAP4430_RM_L3_2_GPMC_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x012c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET		0x0134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define OMAP4430_RM_L3_2_OCMC_RAM_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define OMAP4_RM_DUCATI_RSTCTRL_OFFSET			0x0210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define OMAP4430_RM_DUCATI_RSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define OMAP4_RM_DUCATI_RSTST_OFFSET			0x0214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define OMAP4430_RM_DUCATI_RSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET		0x0224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define OMAP4430_RM_DUCATI_DUCATI_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET		0x0324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define OMAP4430_RM_SDMA_SDMA_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET		0x0424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define OMAP4430_RM_MEMIF_DMM_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET		0x042c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define OMAP4430_RM_MEMIF_EMIF_FW_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x042c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET		0x0434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define OMAP4430_RM_MEMIF_EMIF_1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET		0x043c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define OMAP4430_RM_MEMIF_EMIF_2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x043c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define OMAP4_RM_MEMIF_DLL_CONTEXT_OFFSET		0x0444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define OMAP4430_RM_MEMIF_DLL_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define OMAP4_RM_MEMIF_EMIF_H1_CONTEXT_OFFSET		0x0454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define OMAP4430_RM_MEMIF_EMIF_H1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define OMAP4_RM_MEMIF_EMIF_H2_CONTEXT_OFFSET		0x045c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define OMAP4430_RM_MEMIF_EMIF_H2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x045c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define OMAP4_RM_MEMIF_DLL_H_CONTEXT_OFFSET		0x0464
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define OMAP4430_RM_MEMIF_DLL_H_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET		0x0524
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define OMAP4430_RM_D2D_SAD2D_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define OMAP4_RM_D2D_MODEM_ICR_CONTEXT_OFFSET		0x052c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET		0x0534
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET		0x0624
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define OMAP4430_RM_L4CFG_L4_CFG_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET		0x062c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define OMAP4430_RM_L4CFG_HW_SEM_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x062c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET		0x0634
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define OMAP4430_RM_L4CFG_MAILBOX_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define OMAP4_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET		0x063c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define OMAP4430_RM_L4CFG_SAR_ROM_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x063c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET		0x0724
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define OMAP4430_RM_L3INSTR_L3_3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET	0x072c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define OMAP4430_RM_L3INSTR_L3_INSTR_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x072c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET		0x0744
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define OMAP4430_RM_L3INSTR_OCP_WP1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* PRM.IVAHD_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define OMAP4_PM_IVAHD_PWRSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define OMAP4430_PM_IVAHD_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define OMAP4_PM_IVAHD_PWRSTST_OFFSET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define OMAP4430_PM_IVAHD_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define OMAP4_RM_IVAHD_RSTCTRL_OFFSET			0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define OMAP4430_RM_IVAHD_RSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define OMAP4_RM_IVAHD_RSTST_OFFSET			0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define OMAP4430_RM_IVAHD_RSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET		0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define OMAP4430_RM_IVAHD_IVAHD_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET		0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define OMAP4430_RM_IVAHD_SL2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x002c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* PRM.CAM_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define OMAP4_PM_CAM_PWRSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define OMAP4430_PM_CAM_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define OMAP4_PM_CAM_PWRSTST_OFFSET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define OMAP4430_PM_CAM_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define OMAP4_RM_CAM_ISS_CONTEXT_OFFSET			0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define OMAP4430_RM_CAM_ISS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET		0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define OMAP4430_RM_CAM_FDIF_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x002c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* PRM.DSS_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define OMAP4_PM_DSS_PWRSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define OMAP4430_PM_DSS_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define OMAP4_PM_DSS_PWRSTST_OFFSET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define OMAP4430_PM_DSS_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define OMAP4_PM_DSS_DSS_WKDEP_OFFSET			0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define OMAP4430_PM_DSS_DSS_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define OMAP4_RM_DSS_DSS_CONTEXT_OFFSET			0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define OMAP4430_RM_DSS_DSS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define OMAP4_RM_DSS_DEISS_CONTEXT_OFFSET		0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define OMAP4430_RM_DSS_DEISS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x002c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* PRM.GFX_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define OMAP4_PM_GFX_PWRSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define OMAP4430_PM_GFX_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define OMAP4_PM_GFX_PWRSTST_OFFSET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define OMAP4430_PM_GFX_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define OMAP4_RM_GFX_GFX_CONTEXT_OFFSET			0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define OMAP4430_RM_GFX_GFX_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* PRM.L3INIT_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define OMAP4_PM_L3INIT_PWRSTCTRL_OFFSET		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define OMAP4430_PM_L3INIT_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define OMAP4_PM_L3INIT_PWRSTST_OFFSET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define OMAP4430_PM_L3INIT_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define OMAP4_PM_L3INIT_MMC1_WKDEP_OFFSET		0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define OMAP4430_PM_L3INIT_MMC1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET		0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define OMAP4430_RM_L3INIT_MMC1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x002c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define OMAP4_PM_L3INIT_MMC2_WKDEP_OFFSET		0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define OMAP4430_PM_L3INIT_MMC2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET		0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define OMAP4430_RM_L3INIT_MMC2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define OMAP4_PM_L3INIT_HSI_WKDEP_OFFSET		0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define OMAP4430_PM_L3INIT_HSI_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET		0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define OMAP4430_RM_L3INIT_HSI_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x003c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define OMAP4_PM_L3INIT_UNIPRO1_WKDEP_OFFSET		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define OMAP4430_PM_L3INIT_UNIPRO1_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define OMAP4_RM_L3INIT_UNIPRO1_CONTEXT_OFFSET		0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define OMAP4430_RM_L3INIT_UNIPRO1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define OMAP4_PM_L3INIT_USB_HOST_WKDEP_OFFSET		0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define OMAP4430_PM_L3INIT_USB_HOST_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET		0x005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define OMAP4430_RM_L3INIT_USB_HOST_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x005c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define OMAP4_PM_L3INIT_USB_OTG_WKDEP_OFFSET		0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define OMAP4430_PM_L3INIT_USB_OTG_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET		0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define OMAP4430_RM_L3INIT_USB_OTG_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define OMAP4_PM_L3INIT_USB_TLL_WKDEP_OFFSET		0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define OMAP4430_PM_L3INIT_USB_TLL_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET		0x006c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define OMAP4430_RM_L3INIT_USB_TLL_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x006c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define OMAP4_RM_L3INIT_P1500_CONTEXT_OFFSET		0x007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define OMAP4430_RM_L3INIT_P1500_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x007c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define OMAP4_RM_L3INIT_EMAC_CONTEXT_OFFSET		0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define OMAP4430_RM_L3INIT_EMAC_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define OMAP4_PM_L3INIT_SATA_WKDEP_OFFSET		0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define OMAP4430_PM_L3INIT_SATA_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define OMAP4_RM_L3INIT_SATA_CONTEXT_OFFSET		0x008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define OMAP4430_RM_L3INIT_SATA_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x008c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define OMAP4_RM_L3INIT_TPPSS_CONTEXT_OFFSET		0x0094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define OMAP4430_RM_L3INIT_TPPSS_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define OMAP4_PM_L3INIT_PCIESS_WKDEP_OFFSET		0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define OMAP4430_PM_L3INIT_PCIESS_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define OMAP4_RM_L3INIT_PCIESS_CONTEXT_OFFSET		0x009c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define OMAP4430_RM_L3INIT_PCIESS_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x009c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define OMAP4_RM_L3INIT_CCPTX_CONTEXT_OFFSET		0x00ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define OMAP4430_RM_L3INIT_CCPTX_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00ac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define OMAP4_PM_L3INIT_XHPI_WKDEP_OFFSET		0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define OMAP4430_PM_L3INIT_XHPI_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define OMAP4_RM_L3INIT_XHPI_CONTEXT_OFFSET		0x00c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define OMAP4430_RM_L3INIT_XHPI_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define OMAP4_PM_L3INIT_MMC6_WKDEP_OFFSET		0x00c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define OMAP4430_PM_L3INIT_MMC6_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define OMAP4_RM_L3INIT_MMC6_CONTEXT_OFFSET		0x00cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define OMAP4430_RM_L3INIT_MMC6_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define OMAP4_PM_L3INIT_USB_HOST_FS_WKDEP_OFFSET	0x00d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define OMAP4430_PM_L3INIT_USB_HOST_FS_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET	0x00d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define OMAP4430_RM_L3INIT_USB_HOST_FS_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00d4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET	0x00e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define OMAP4430_RM_L3INIT_USBPHYOCP2SCP_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00e4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* PRM.L4PER_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define OMAP4_PM_L4PER_PWRSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define OMAP4430_PM_L4PER_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define OMAP4_PM_L4PER_PWRSTST_OFFSET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define OMAP4430_PM_L4PER_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define OMAP4_RM_L4PER_ADC_CONTEXT_OFFSET		0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define OMAP4430_RM_L4PER_ADC_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define OMAP4_PM_L4PER_DMTIMER10_WKDEP_OFFSET		0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define OMAP4430_PM_L4PER_DMTIMER10_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET		0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define OMAP4430_RM_L4PER_DMTIMER10_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x002c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define OMAP4_PM_L4PER_DMTIMER11_WKDEP_OFFSET		0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define OMAP4430_PM_L4PER_DMTIMER11_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET		0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define OMAP4430_RM_L4PER_DMTIMER11_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define OMAP4_PM_L4PER_DMTIMER2_WKDEP_OFFSET		0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define OMAP4430_PM_L4PER_DMTIMER2_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET		0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define OMAP4430_RM_L4PER_DMTIMER2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x003c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define OMAP4_PM_L4PER_DMTIMER3_WKDEP_OFFSET		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define OMAP4430_PM_L4PER_DMTIMER3_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET		0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define OMAP4430_RM_L4PER_DMTIMER3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define OMAP4_PM_L4PER_DMTIMER4_WKDEP_OFFSET		0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define OMAP4430_PM_L4PER_DMTIMER4_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET		0x004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define OMAP4430_RM_L4PER_DMTIMER4_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x004c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define OMAP4_PM_L4PER_DMTIMER9_WKDEP_OFFSET		0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define OMAP4430_PM_L4PER_DMTIMER9_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET		0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define OMAP4430_RM_L4PER_DMTIMER9_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET		0x005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define OMAP4430_RM_L4PER_ELM_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x005c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define OMAP4_PM_L4PER_GPIO2_WKDEP_OFFSET		0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define OMAP4430_PM_L4PER_GPIO2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET		0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define OMAP4430_RM_L4PER_GPIO2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define OMAP4_PM_L4PER_GPIO3_WKDEP_OFFSET		0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define OMAP4430_PM_L4PER_GPIO3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET		0x006c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define OMAP4430_RM_L4PER_GPIO3_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x006c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define OMAP4_PM_L4PER_GPIO4_WKDEP_OFFSET		0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define OMAP4430_PM_L4PER_GPIO4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET		0x0074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define OMAP4430_RM_L4PER_GPIO4_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define OMAP4_PM_L4PER_GPIO5_WKDEP_OFFSET		0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define OMAP4430_PM_L4PER_GPIO5_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET		0x007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define OMAP4430_RM_L4PER_GPIO5_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x007c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define OMAP4_PM_L4PER_GPIO6_WKDEP_OFFSET		0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define OMAP4430_PM_L4PER_GPIO6_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET		0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define OMAP4430_RM_L4PER_GPIO6_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET		0x008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define OMAP4430_RM_L4PER_HDQ1W_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x008c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define OMAP4_PM_L4PER_HECC1_WKDEP_OFFSET		0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define OMAP4430_PM_L4PER_HECC1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define OMAP4_RM_L4PER_HECC1_CONTEXT_OFFSET		0x0094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define OMAP4430_RM_L4PER_HECC1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define OMAP4_PM_L4PER_HECC2_WKDEP_OFFSET		0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define OMAP4430_PM_L4PER_HECC2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define OMAP4_RM_L4PER_HECC2_CONTEXT_OFFSET		0x009c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define OMAP4430_RM_L4PER_HECC2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x009c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define OMAP4_PM_L4PER_I2C1_WKDEP_OFFSET		0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define OMAP4430_PM_L4PER_I2C1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET		0x00a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define OMAP4430_RM_L4PER_I2C1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define OMAP4_PM_L4PER_I2C2_WKDEP_OFFSET		0x00a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define OMAP4430_PM_L4PER_I2C2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET		0x00ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define OMAP4430_RM_L4PER_I2C2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00ac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define OMAP4_PM_L4PER_I2C3_WKDEP_OFFSET		0x00b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define OMAP4430_PM_L4PER_I2C3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET		0x00b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define OMAP4430_RM_L4PER_I2C3_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define OMAP4_PM_L4PER_I2C4_WKDEP_OFFSET		0x00b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define OMAP4430_PM_L4PER_I2C4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET		0x00bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define OMAP4430_RM_L4PER_I2C4_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00bc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET		0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define OMAP4430_RM_L4PER_L4_PER_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define OMAP4_PM_L4PER_MCASP2_WKDEP_OFFSET		0x00d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define OMAP4430_PM_L4PER_MCASP2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define OMAP4_RM_L4PER_MCASP2_CONTEXT_OFFSET		0x00d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define OMAP4430_RM_L4PER_MCASP2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define OMAP4_PM_L4PER_MCASP3_WKDEP_OFFSET		0x00d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define OMAP4430_PM_L4PER_MCASP3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define OMAP4_RM_L4PER_MCASP3_CONTEXT_OFFSET		0x00dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define OMAP4430_RM_L4PER_MCASP3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define OMAP4_PM_L4PER_MCBSP4_WKDEP_OFFSET		0x00e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define OMAP4430_PM_L4PER_MCBSP4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00e0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET		0x00e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define OMAP4430_RM_L4PER_MCBSP4_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00e4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define OMAP4_RM_L4PER_MGATE_CONTEXT_OFFSET		0x00ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define OMAP4430_RM_L4PER_MGATE_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00ec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define OMAP4_PM_L4PER_MCSPI1_WKDEP_OFFSET		0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define OMAP4430_PM_L4PER_MCSPI1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET		0x00f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define OMAP4430_RM_L4PER_MCSPI1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define OMAP4_PM_L4PER_MCSPI2_WKDEP_OFFSET		0x00f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define OMAP4430_PM_L4PER_MCSPI2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET		0x00fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define OMAP4430_RM_L4PER_MCSPI2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00fc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define OMAP4_PM_L4PER_MCSPI3_WKDEP_OFFSET		0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define OMAP4430_PM_L4PER_MCSPI3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET		0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define OMAP4430_RM_L4PER_MCSPI3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define OMAP4_PM_L4PER_MCSPI4_WKDEP_OFFSET		0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define OMAP4430_PM_L4PER_MCSPI4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET		0x010c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define OMAP4430_RM_L4PER_MCSPI4_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x010c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define OMAP4_PM_L4PER_MMCSD3_WKDEP_OFFSET		0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define OMAP4430_PM_L4PER_MMCSD3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET		0x0124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define OMAP4430_RM_L4PER_MMCSD3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define OMAP4_PM_L4PER_MMCSD4_WKDEP_OFFSET		0x0128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define OMAP4430_PM_L4PER_MMCSD4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET		0x012c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define OMAP4430_RM_L4PER_MMCSD4_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x012c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define OMAP4_RM_L4PER_MSPROHG_CONTEXT_OFFSET		0x0134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define OMAP4430_RM_L4PER_MSPROHG_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define OMAP4_PM_L4PER_SLIMBUS2_WKDEP_OFFSET		0x0138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define OMAP4430_PM_L4PER_SLIMBUS2_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET		0x013c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define OMAP4430_RM_L4PER_SLIMBUS2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x013c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define OMAP4_PM_L4PER_UART1_WKDEP_OFFSET		0x0140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define OMAP4430_PM_L4PER_UART1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET		0x0144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define OMAP4430_RM_L4PER_UART1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define OMAP4_PM_L4PER_UART2_WKDEP_OFFSET		0x0148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define OMAP4430_PM_L4PER_UART2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET		0x014c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define OMAP4430_RM_L4PER_UART2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x014c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define OMAP4_PM_L4PER_UART3_WKDEP_OFFSET		0x0150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define OMAP4430_PM_L4PER_UART3_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET		0x0154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define OMAP4430_RM_L4PER_UART3_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define OMAP4_PM_L4PER_UART4_WKDEP_OFFSET		0x0158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define OMAP4430_PM_L4PER_UART4_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET		0x015c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define OMAP4430_RM_L4PER_UART4_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x015c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define OMAP4_PM_L4PER_MMCSD5_WKDEP_OFFSET		0x0160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define OMAP4430_PM_L4PER_MMCSD5_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET		0x0164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define OMAP4430_RM_L4PER_MMCSD5_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define OMAP4_PM_L4PER_I2C5_WKDEP_OFFSET		0x0168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define OMAP4430_PM_L4PER_I2C5_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define OMAP4_RM_L4PER_I2C5_CONTEXT_OFFSET		0x016c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define OMAP4430_RM_L4PER_I2C5_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x016c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET		0x01a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define OMAP4430_RM_L4SEC_AES1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01a4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET		0x01ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define OMAP4430_RM_L4SEC_AES2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01ac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET		0x01b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define OMAP4430_RM_L4SEC_DES3DES_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01b4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define OMAP4_RM_L4SEC_PKAEIP29_CONTEXT_OFFSET		0x01bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define OMAP4430_RM_L4SEC_PKAEIP29_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01bc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define OMAP4_RM_L4SEC_RNG_CONTEXT_OFFSET		0x01c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define OMAP4430_RM_L4SEC_RNG_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01c4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET		0x01cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define OMAP4430_RM_L4SEC_SHA2MD51_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define OMAP4_RM_L4SEC_CRYPTODMA_CONTEXT_OFFSET		0x01dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define OMAP4430_RM_L4SEC_CRYPTODMA_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* PRM.CEFUSE_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define OMAP4_PM_CEFUSE_PWRSTCTRL_OFFSET		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define OMAP4430_PM_CEFUSE_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define OMAP4_PM_CEFUSE_PWRSTST_OFFSET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define OMAP4430_PM_CEFUSE_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define OMAP4_RM_CEFUSE_CEFUSE_CONTEXT_OFFSET		0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define OMAP4430_RM_CEFUSE_CEFUSE_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* PRM.WKUP_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET		0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define OMAP4430_RM_WKUP_L4WKUP_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define OMAP4_RM_WKUP_WDT1_CONTEXT_OFFSET		0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define OMAP4430_RM_WKUP_WDT1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x002c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define OMAP4_PM_WKUP_WDT2_WKDEP_OFFSET			0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define OMAP4430_PM_WKUP_WDT2_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET		0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define OMAP4430_RM_WKUP_WDT2_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define OMAP4_PM_WKUP_GPIO1_WKDEP_OFFSET		0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define OMAP4430_PM_WKUP_GPIO1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET		0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define OMAP4430_RM_WKUP_GPIO1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x003c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define OMAP4_PM_WKUP_TIMER1_WKDEP_OFFSET		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define OMAP4430_PM_WKUP_TIMER1_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET		0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define OMAP4430_RM_WKUP_TIMER1_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define OMAP4_PM_WKUP_TIMER12_WKDEP_OFFSET		0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define OMAP4430_PM_WKUP_TIMER12_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define OMAP4_RM_WKUP_TIMER12_CONTEXT_OFFSET		0x004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define OMAP4430_RM_WKUP_TIMER12_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x004c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET		0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define OMAP4430_RM_WKUP_SYNCTIMER_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define OMAP4_PM_WKUP_USIM_WKDEP_OFFSET			0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define OMAP4430_PM_WKUP_USIM_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define OMAP4_RM_WKUP_USIM_CONTEXT_OFFSET		0x005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define OMAP4430_RM_WKUP_USIM_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x005c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define OMAP4_RM_WKUP_SARRAM_CONTEXT_OFFSET		0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define OMAP4430_RM_WKUP_SARRAM_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define OMAP4_PM_WKUP_KEYBOARD_WKDEP_OFFSET		0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define OMAP4430_PM_WKUP_KEYBOARD_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET		0x007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define OMAP4430_RM_WKUP_KEYBOARD_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x007c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define OMAP4_PM_WKUP_RTC_WKDEP_OFFSET			0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define OMAP4430_PM_WKUP_RTC_WKDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define OMAP4_RM_WKUP_RTC_CONTEXT_OFFSET		0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define OMAP4430_RM_WKUP_RTC_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* PRM.WKUP_CM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define OMAP4_CM_WKUP_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define OMAP4430_CM_WKUP_CLKSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define OMAP4430_CM_WKUP_L4WKUP_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define OMAP4_CM_WKUP_WDT1_CLKCTRL_OFFSET		0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define OMAP4430_CM_WKUP_WDT1_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET		0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define OMAP4430_CM_WKUP_WDT2_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET		0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define OMAP4430_CM_WKUP_GPIO1_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define OMAP4430_CM_WKUP_TIMER1_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define OMAP4_CM_WKUP_TIMER12_CLKCTRL_OFFSET		0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define OMAP4430_CM_WKUP_TIMER12_CLKCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET		0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define OMAP4_CM_WKUP_USIM_CLKCTRL_OFFSET		0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define OMAP4430_CM_WKUP_USIM_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define OMAP4_CM_WKUP_SARRAM_CLKCTRL_OFFSET		0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define OMAP4430_CM_WKUP_SARRAM_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET		0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define OMAP4_CM_WKUP_RTC_CLKCTRL_OFFSET		0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define OMAP4430_CM_WKUP_RTC_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET		0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define OMAP4430_CM_WKUP_BANDGAP_CLKCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* PRM.EMU_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define OMAP4_PM_EMU_PWRSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define OMAP4430_PM_EMU_PWRSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define OMAP4_PM_EMU_PWRSTST_OFFSET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define OMAP4430_PM_EMU_PWRSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET		0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define OMAP4430_RM_EMU_DEBUGSS_CONTEXT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /* PRM.EMU_CM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define OMAP4_CM_EMU_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define OMAP4430_CM_EMU_CLKSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define OMAP4_CM_EMU_DYNAMICDEP_OFFSET			0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define OMAP4430_CM_EMU_DYNAMICDEP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define OMAP4430_CM_EMU_DEBUGSS_CLKCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* PRM.DEVICE_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define OMAP4_PRM_RSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define OMAP4430_PRM_RSTCTRL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define OMAP4_PRM_RSTST_OFFSET				0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define OMAP4430_PRM_RSTST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define OMAP4_PRM_RSTTIME_OFFSET			0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define OMAP4430_PRM_RSTTIME				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define OMAP4_PRM_CLKREQCTRL_OFFSET			0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define OMAP4430_PRM_CLKREQCTRL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define OMAP4_PRM_VOLTCTRL_OFFSET			0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define OMAP4430_PRM_VOLTCTRL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define OMAP4_PRM_PWRREQCTRL_OFFSET			0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define OMAP4430_PRM_PWRREQCTRL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define OMAP4_PRM_PSCON_COUNT_OFFSET			0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define OMAP4430_PRM_PSCON_COUNT			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define OMAP4_PRM_IO_COUNT_OFFSET			0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define OMAP4430_PRM_IO_COUNT				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x001c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define OMAP4_PRM_IO_PMCTRL_OFFSET			0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define OMAP4430_PRM_IO_PMCTRL				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define OMAP4_PRM_VOLTSETUP_WARMRESET_OFFSET		0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define OMAP4430_PRM_VOLTSETUP_WARMRESET		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define OMAP4_PRM_VOLTSETUP_CORE_OFF_OFFSET		0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define OMAP4430_PRM_VOLTSETUP_CORE_OFF			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define OMAP4_PRM_VOLTSETUP_MPU_OFF_OFFSET		0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define OMAP4430_PRM_VOLTSETUP_MPU_OFF			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x002c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define OMAP4_PRM_VOLTSETUP_IVA_OFF_OFFSET		0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define OMAP4430_PRM_VOLTSETUP_IVA_OFF			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET	0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define OMAP4430_PRM_VOLTSETUP_CORE_RET_SLEEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET	0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define OMAP4430_PRM_VOLTSETUP_MPU_RET_SLEEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET	0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define OMAP4430_PRM_VOLTSETUP_IVA_RET_SLEEP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x003c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define OMAP4_PRM_VP_CORE_CONFIG_OFFSET			0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define OMAP4430_PRM_VP_CORE_CONFIG			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define OMAP4_PRM_VP_CORE_STATUS_OFFSET			0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define OMAP4430_PRM_VP_CORE_STATUS			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET		0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define OMAP4430_PRM_VP_CORE_VLIMITTO			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET		0x004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define OMAP4430_PRM_VP_CORE_VOLTAGE			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x004c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET		0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define OMAP4430_PRM_VP_CORE_VSTEPMAX			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET		0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define OMAP4430_PRM_VP_CORE_VSTEPMIN			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define OMAP4_PRM_VP_MPU_CONFIG_OFFSET			0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define OMAP4430_PRM_VP_MPU_CONFIG			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define OMAP4_PRM_VP_MPU_STATUS_OFFSET			0x005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define OMAP4430_PRM_VP_MPU_STATUS			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x005c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET		0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define OMAP4430_PRM_VP_MPU_VLIMITTO			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET			0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define OMAP4430_PRM_VP_MPU_VOLTAGE			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET		0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define OMAP4430_PRM_VP_MPU_VSTEPMAX			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET		0x006c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define OMAP4430_PRM_VP_MPU_VSTEPMIN			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x006c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define OMAP4_PRM_VP_IVA_CONFIG_OFFSET			0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define OMAP4430_PRM_VP_IVA_CONFIG			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define OMAP4_PRM_VP_IVA_STATUS_OFFSET			0x0074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define OMAP4430_PRM_VP_IVA_STATUS			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET		0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define OMAP4430_PRM_VP_IVA_VLIMITTO			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET			0x007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define OMAP4430_PRM_VP_IVA_VOLTAGE			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x007c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET		0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define OMAP4430_PRM_VP_IVA_VSTEPMAX			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET		0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define OMAP4430_PRM_VP_IVA_VSTEPMIN			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define OMAP4_PRM_VC_SMPS_SA_OFFSET			0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define OMAP4430_PRM_VC_SMPS_SA				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET		0x008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define OMAP4430_PRM_VC_VAL_SMPS_RA_VOL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x008c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET		0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define OMAP4430_PRM_VC_VAL_SMPS_RA_CMD			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET		0x0094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET		0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define OMAP4430_PRM_VC_VAL_CMD_VDD_MPU_L		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET		0x009c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define OMAP4430_PRM_VC_VAL_CMD_VDD_IVA_L		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x009c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define OMAP4_PRM_VC_VAL_BYPASS_OFFSET			0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define OMAP4430_PRM_VC_VAL_BYPASS			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET			0x00a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define OMAP4430_PRM_VC_CFG_CHANNEL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET		0x00a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define OMAP4430_PRM_VC_CFG_I2C_MODE			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET			0x00ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define OMAP4430_PRM_VC_CFG_I2C_CLK			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define OMAP4_PRM_SRAM_COUNT_OFFSET			0x00b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define OMAP4430_PRM_SRAM_COUNT				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define OMAP4_PRM_SRAM_WKUP_SETUP_OFFSET		0x00b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define OMAP4430_PRM_SRAM_WKUP_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define OMAP4_PRM_LDO_SRAM_CORE_SETUP_OFFSET		0x00b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define OMAP4430_PRM_LDO_SRAM_CORE_SETUP		OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define OMAP4_PRM_LDO_SRAM_CORE_CTRL_OFFSET		0x00bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define OMAP4430_PRM_LDO_SRAM_CORE_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00bc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define OMAP4_PRM_LDO_SRAM_MPU_SETUP_OFFSET		0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define OMAP4430_PRM_LDO_SRAM_MPU_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define OMAP4_PRM_LDO_SRAM_MPU_CTRL_OFFSET		0x00c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define OMAP4430_PRM_LDO_SRAM_MPU_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define OMAP4_PRM_LDO_SRAM_IVA_SETUP_OFFSET		0x00c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define OMAP4430_PRM_LDO_SRAM_IVA_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define OMAP4_PRM_LDO_SRAM_IVA_CTRL_OFFSET		0x00cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define OMAP4430_PRM_LDO_SRAM_IVA_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define OMAP4_PRM_LDO_ABB_MPU_SETUP_OFFSET		0x00d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define OMAP4430_PRM_LDO_ABB_MPU_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define OMAP4_PRM_LDO_ABB_MPU_CTRL_OFFSET		0x00d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define OMAP4430_PRM_LDO_ABB_MPU_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define OMAP4_PRM_LDO_ABB_IVA_SETUP_OFFSET		0x00d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define OMAP4430_PRM_LDO_ABB_IVA_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET		0x00dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define OMAP4430_PRM_LDO_ABB_IVA_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define OMAP4_PRM_LDO_BANDGAP_SETUP_OFFSET		0x00e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define OMAP4430_PRM_LDO_BANDGAP_SETUP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET		0x00e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define OMAP4430_PRM_DEVICE_OFF_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define OMAP4_PRM_PHASE1_CNDP_OFFSET			0x00e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define OMAP4430_PRM_PHASE1_CNDP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define OMAP4_PRM_PHASE2A_CNDP_OFFSET			0x00ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define OMAP4430_PRM_PHASE2A_CNDP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define OMAP4_PRM_PHASE2B_CNDP_OFFSET			0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define OMAP4430_PRM_PHASE2B_CNDP			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define OMAP4_PRM_MODEM_IF_CTRL_OFFSET			0x00f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define OMAP4430_PRM_MODEM_IF_CTRL			OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define OMAP4_PRM_VC_ERRST_OFFSET			0x00f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define OMAP4430_PRM_VC_ERRST				OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #endif