^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP3xxx Power/Reset Management (PRM) register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2008-2010 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Paul Walmsley
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * The PRM hardware modules on the OMAP2/3 are quite similar to each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * other. The PRM on OMAP4 has a new register layout, and is handled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * in a separate file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef __ARCH_ARM_MACH_OMAP2_PRM3XXX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define __ARCH_ARM_MACH_OMAP2_PRM3XXX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "prcm-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "prm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "prm2xxx_3xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define OMAP34XX_PRM_REGADDR(module, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * OMAP3-specific global PRM registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Use {read,write}l_relaxed() with these registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * With a few exceptions, these are the register names beginning with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * PRM_* on 34xx. (The exceptions are the IRQSTATUS and IRQENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * bits.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OMAP3_PRM_REVISION_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OMAP3_PRM_VC_CMD_VAL_0_OFFSET 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OMAP3430_PRM_VC_CMD_VAL_0 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OMAP3_PRM_VC_CMD_VAL_1_OFFSET 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OMAP3430_PRM_VC_CMD_VAL_1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OMAP3_PRM_VC_CH_CONF_OFFSET 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OMAP3430_PRM_VC_CH_CONF OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OMAP3_PRM_VC_I2C_CFG_OFFSET 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OMAP3430_PRM_VC_I2C_CFG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OMAP3_PRM_VC_BYPASS_VAL_OFFSET 0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OMAP3430_PRM_VC_BYPASS_VAL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OMAP3_PRM_RSTCTRL_OFFSET 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OMAP3430_PRM_RSTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OMAP3_PRM_RSTTIME_OFFSET 0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OMAP3430_PRM_RSTTIME OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OMAP3_PRM_RSTST_OFFSET 0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OMAP3430_PRM_RSTST OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OMAP3_PRM_VOLTCTRL_OFFSET 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OMAP3430_PRM_VOLTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OMAP3_PRM_SRAM_PCHARGE_OFFSET 0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OMAP3430_PRM_SRAM_PCHARGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OMAP3_PRM_CLKSRC_CTRL_OFFSET 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OMAP3430_PRM_CLKSRC_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OMAP3_PRM_VOLTSETUP1_OFFSET 0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OMAP3430_PRM_VOLTSETUP1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OMAP3_PRM_VOLTOFFSET_OFFSET 0x0094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OMAP3430_PRM_VOLTOFFSET OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OMAP3_PRM_CLKSETUP_OFFSET 0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define OMAP3430_PRM_CLKSETUP OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OMAP3_PRM_POLCTRL_OFFSET 0x009c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OMAP3430_PRM_POLCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OMAP3_PRM_VOLTSETUP2_OFFSET 0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OMAP3430_PRM_VOLTSETUP2 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OMAP3_PRM_VP1_CONFIG_OFFSET 0x00b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OMAP3430_PRM_VP1_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OMAP3_PRM_VP1_VSTEPMIN_OFFSET 0x00b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OMAP3430_PRM_VP1_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OMAP3_PRM_VP1_VSTEPMAX_OFFSET 0x00b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define OMAP3430_PRM_VP1_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define OMAP3_PRM_VP1_VLIMITTO_OFFSET 0x00bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define OMAP3430_PRM_VP1_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define OMAP3_PRM_VP1_VOLTAGE_OFFSET 0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define OMAP3430_PRM_VP1_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define OMAP3_PRM_VP1_STATUS_OFFSET 0x00c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define OMAP3430_PRM_VP1_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define OMAP3_PRM_VP2_CONFIG_OFFSET 0x00d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define OMAP3430_PRM_VP2_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define OMAP3_PRM_VP2_VSTEPMIN_OFFSET 0x00d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OMAP3430_PRM_VP2_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define OMAP3_PRM_VP2_VSTEPMAX_OFFSET 0x00d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define OMAP3430_PRM_VP2_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define OMAP3_PRM_VP2_VLIMITTO_OFFSET 0x00dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define OMAP3430_PRM_VP2_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define OMAP3_PRM_VP2_VOLTAGE_OFFSET 0x00e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define OMAP3430_PRM_VP2_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define OMAP3_PRM_VP2_STATUS_OFFSET 0x00e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define OMAP3430_PRM_VP2_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define OMAP3_PRM_CLKSEL_OFFSET 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define OMAP3430_PRM_CLKSEL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define OMAP3_PRM_CLKOUT_CTRL_OFFSET 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define OMAP3430_PRM_CLKOUT_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* OMAP3 specific register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define OMAP3430ES2_PM_WKEN3 0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define OMAP3430ES2_PM_WKST3 0x00b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define OMAP3430_PM_MPUGRPSEL 0x00a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define OMAP3430ES2_PM_MPUGRPSEL3 0x00f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define OMAP3430_PM_IVAGRPSEL 0x00a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define OMAP3430ES2_PM_IVAGRPSEL3 0x00f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define OMAP3430_PM_PREPWSTST 0x00e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #ifndef __ASSEMBLER__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * OMAP3 access functions for voltage controller (VC) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * voltage proccessor (VP) in the PRM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) extern u32 omap3_prm_vcvp_read(u8 offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) extern void omap3_prm_vcvp_write(u32 val, u8 offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int __init omap3xxx_prm_init(const struct omap_prcm_init_data *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) void omap3xxx_prm_iva_idle(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) void omap3_prm_reset_modem(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int omap3xxx_prm_clear_global_cold_reset(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) void omap3_prm_save_scratchpad_contents(u32 *ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) void omap3_prm_init_pm(bool has_uart4, bool has_iva);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #endif /* __ASSEMBLER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags