^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * AM33XX PRM instance offset macros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #ifndef __ARCH_ARM_MACH_OMAP2_PRM33XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define __ARCH_ARM_MACH_OMAP2_PRM33XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "prcm-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "prm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AM33XX_PRM_BASE 0x44E00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AM33XX_PRM_REGADDR(inst, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRM_BASE + (inst) + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* PRM instances */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AM33XX_PRM_OCP_SOCKET_MOD 0x0B00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AM33XX_PRM_PER_MOD 0x0C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AM33XX_PRM_WKUP_MOD 0x0D00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AM33XX_PRM_MPU_MOD 0x0E00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AM33XX_PRM_DEVICE_MOD 0x0F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AM33XX_PRM_RTC_MOD 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AM33XX_PRM_GFX_MOD 0x1100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AM33XX_PRM_CEFUSE_MOD 0x1200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* PRM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* PRM.OCP_SOCKET_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AM33XX_REVISION_PRM_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AM33XX_REVISION_PRM AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AM33XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AM33XX_PRM_IRQSTATUS_MPU AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AM33XX_PRM_IRQENABLE_MPU_OFFSET 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AM33XX_PRM_IRQENABLE_MPU AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AM33XX_PRM_IRQSTATUS_M3_OFFSET 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AM33XX_PRM_IRQSTATUS_M3 AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AM33XX_PRM_IRQENABLE_M3_OFFSET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AM33XX_PRM_IRQENABLE_M3 AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* PRM.PER_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AM33XX_RM_PER_RSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AM33XX_RM_PER_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AM33XX_PM_PER_PWRSTST_OFFSET 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AM33XX_PM_PER_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AM33XX_PM_PER_PWRSTCTRL_OFFSET 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AM33XX_PM_PER_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* PRM.WKUP_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AM33XX_RM_WKUP_RSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AM33XX_RM_WKUP_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AM33XX_PM_WKUP_PWRSTCTRL_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AM33XX_PM_WKUP_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AM33XX_PM_WKUP_PWRSTST_OFFSET 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AM33XX_PM_WKUP_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define AM33XX_RM_WKUP_RSTST_OFFSET 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AM33XX_RM_WKUP_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* PRM.MPU_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define AM33XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AM33XX_PM_MPU_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AM33XX_PM_MPU_PWRSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define AM33XX_PM_MPU_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define AM33XX_RM_MPU_RSTST_OFFSET 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AM33XX_RM_MPU_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* PRM.DEVICE_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define AM33XX_PRM_RSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define AM33XX_PRM_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define AM33XX_PRM_RSTTIME_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define AM33XX_PRM_RSTTIME AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define AM33XX_PRM_RSTST_OFFSET 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define AM33XX_PRM_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define AM33XX_PRM_SRAM_COUNT_OFFSET 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define AM33XX_PRM_SRAM_COUNT AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define AM33XX_PRM_LDO_SRAM_CORE_SETUP_OFFSET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define AM33XX_PRM_LDO_SRAM_CORE_SETUP AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define AM33XX_PRM_LDO_SRAM_CORE_CTRL_OFFSET 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define AM33XX_PRM_LDO_SRAM_CORE_CTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define AM33XX_PRM_LDO_SRAM_MPU_SETUP_OFFSET 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define AM33XX_PRM_LDO_SRAM_MPU_SETUP AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define AM33XX_PRM_LDO_SRAM_MPU_CTRL_OFFSET 0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define AM33XX_PRM_LDO_SRAM_MPU_CTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x001c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* PRM.RTC_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define AM33XX_PM_RTC_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define AM33XX_PM_RTC_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define AM33XX_PM_RTC_PWRSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define AM33XX_PM_RTC_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* PRM.GFX_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define AM33XX_PM_GFX_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define AM33XX_PM_GFX_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define AM33XX_RM_GFX_RSTCTRL_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define AM33XX_RM_GFX_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define AM33XX_PM_GFX_PWRSTST_OFFSET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define AM33XX_PM_GFX_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define AM33XX_RM_GFX_RSTST_OFFSET 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define AM33XX_RM_GFX_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* PRM.CEFUSE_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define AM33XX_PM_CEFUSE_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define AM33XX_PM_CEFUSE_PWRSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define AM33XX_PM_CEFUSE_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #ifndef __ASSEMBLER__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int am33xx_prm_init(const struct omap_prcm_init_data *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #endif /* ASSEMBLER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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