^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP2xxx/3xxx-common Power/Reset Management (PRM) register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2008-2010 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Paul Walmsley
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * The PRM hardware modules on the OMAP2/3 are quite similar to each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * other. The PRM on OMAP4 has a new register layout, and is handled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * in a separate file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "prcm-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "prm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Module specific PRM register offsets from PRM_BASE + domain offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Use prm_{read,write}_mod_reg() with these registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * With a few exceptions, these are the register names beginning with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * {PM,RM}_* on both OMAP2/3 SoC families.. (The exceptions are the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * IRQSTATUS and IRQENABLE bits.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Register offsets appearing on both OMAP2 and OMAP3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OMAP2_RM_RSTCTRL 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OMAP2_RM_RSTTIME 0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OMAP2_RM_RSTST 0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OMAP2_PM_PWSTCTRL 0x00e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OMAP2_PM_PWSTST 0x00e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PM_WKEN 0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PM_WKEN1 PM_WKEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PM_WKST 0x00b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PM_WKST1 PM_WKST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PM_WKDEP 0x00c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PM_EVGENCTRL 0x00d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PM_EVGENONTIM 0x00d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PM_EVGENOFFTIM 0x00dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #ifndef __ASSEMBLER__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include "powerdomain.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Power/reset management domain register get/set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return readl_relaxed(prm_base.va + module + idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) writel_relaxed(val, prm_base.va + module + idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Read-modify-write a register in a PRM module. Caller must lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static inline u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) s16 idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) v = omap2_prm_read_mod_reg(module, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) v &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) v |= bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) omap2_prm_write_mod_reg(v, module, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Read a PRM register, AND it, and shift the result down to bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static inline u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) v = omap2_prm_read_mod_reg(domain, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) v &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) v >>= __ffs(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static inline u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static inline u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* These omap2_ PRM functions apply to both OMAP2 and 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int omap2_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int omap2_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u16 offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int omap2_prm_deassert_hardreset(u8 rst_shift, u8 st_shift, u8 part,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) s16 prm_mod, u16 reset_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u16 st_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) extern int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) extern int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) extern int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) extern int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u8 pwrst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) extern int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u8 pwrst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) extern int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) extern int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) extern int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) extern int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) extern int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct clockdomain *clkdm2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) extern int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct clockdomain *clkdm2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) extern int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct clockdomain *clkdm2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) extern int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #endif /* __ASSEMBLER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * Bits common to specific registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * The 3430 register and bit names are generally used,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * since they tend to make more sense
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* PM_EVGENONTIM_MPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Named PM_EVEGENONTIM_MPU on the 24XX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define OMAP_ONTIMEVAL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define OMAP_ONTIMEVAL_MASK (0xffffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* PM_EVGENOFFTIM_MPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Named PM_EVEGENOFFTIM_MPU on the 24XX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define OMAP_OFFTIMEVAL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define OMAP_OFFTIMEVAL_MASK (0xffffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* PRM_CLKSETUP and PRCM_VOLTSETUP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Named PRCM_CLKSSETUP on the 24XX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define OMAP_SETUP_TIME_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define OMAP_SETUP_TIME_MASK (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* PRM_CLKSRC_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Named PRCM_CLKSRC_CTRL on the 24XX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define OMAP_SYSCLKDIV_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define OMAP_SYSCLKDIV_MASK (0x3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define OMAP_SYSCLKDIV_WIDTH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define OMAP_AUTOEXTCLKMODE_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define OMAP_AUTOEXTCLKMODE_MASK (0x3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define OMAP_SYSCLKSEL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define OMAP_SYSCLKSEL_MASK (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* PM_EVGENCTRL_MPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define OMAP_OFFLOADMODE_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define OMAP_OFFLOADMODE_MASK (0x3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define OMAP_ONLOADMODE_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define OMAP_ONLOADMODE_MASK (0x3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define OMAP_ENABLE_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* PRM_RSTTIME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Named RM_RSTTIME_WKUP on the 24xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define OMAP_RSTTIME2_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define OMAP_RSTTIME2_MASK (0x1f << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define OMAP_RSTTIME1_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define OMAP_RSTTIME1_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* PRM_RSTCTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Named RM_RSTCTRL_WKUP on the 24xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* 2420 calls RST_DPLL3 'RST_DPLL' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define OMAP_RST_DPLL3_MASK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define OMAP_RST_GS_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * Bits common to module-shared registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * Not all registers of a particular type support all of these bits -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * check TRM if you are unsure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * called 'COREWKUP_RST'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define OMAP_COREDOMAINWKUP_RST_MASK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * 2430: RM_RSTST_MDM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * 3430: RM_RSTST_CORE, RM_RSTST_EMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define OMAP_DOMAINWKUP_RST_MASK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * 2430: RM_RSTST_MDM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * 3430: RM_RSTST_CORE, RM_RSTST_EMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define OMAP_GLOBALWARM_RST_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define OMAP_GLOBALWARM_RST_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define OMAP_GLOBALCOLD_RST_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define OMAP_GLOBALCOLD_RST_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * 2430: PM_WKDEP_MDM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * PM_WKDEP_PER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define OMAP_EN_WKUP_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define OMAP_EN_WKUP_MASK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * PM_PWSTCTRL_DSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * 2430: PM_PWSTCTRL_MDM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * PM_PWSTCTRL_NEON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define OMAP_LOGICRETSTATE_MASK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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