^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP2/3 PRM module functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010-2011 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2010 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Benoît Cousson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Paul Walmsley
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "powerdomain.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "prm2xxx_3xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "prm-regbits-24xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "clockdomain.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * omap2_prm_is_hardreset_asserted - read the HW reset line state of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * submodules contained in the hwmod module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * @shift: register bit shift corresponding to the reset line to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * @part: PRM partition, ignored for OMAP2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * @prm_mod: PRM submodule base (e.g. CORE_MOD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * @offset: register offset, ignored for OMAP2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Returns 1 if the (sub)module hardreset line is currently asserted,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * 0 if the (sub)module hardreset line is not currently asserted, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * -EINVAL if called while running on a non-OMAP2/3 chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) int omap2_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) return omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) (1 << shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * omap2_prm_assert_hardreset - assert the HW reset line of a submodule
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * @shift: register bit shift corresponding to the reset line to assert
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * @part: PRM partition, ignored for OMAP2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * @prm_mod: PRM submodule base (e.g. CORE_MOD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @offset: register offset, ignored for OMAP2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * Some IPs like dsp or iva contain processors that require an HW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * reset line to be asserted / deasserted in order to fully enable the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * IP. These modules may have multiple hard-reset lines that reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * different 'submodules' inside the IP block. This function will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * place the submodule into reset. Returns 0 upon success or -EINVAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * upon an argument error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int omap2_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod, u16 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) mask = 1 << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) omap2_prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * omap2_prm_deassert_hardreset - deassert a submodule hardreset line and wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * @prm_mod: PRM submodule base (e.g. CORE_MOD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * @rst_shift: register bit shift corresponding to the reset line to deassert
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @st_shift: register bit shift for the status of the deasserted submodule
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * @part: PRM partition, not used for OMAP2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * @prm_mod: PRM submodule base (e.g. CORE_MOD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * @rst_offset: reset register offset, not used for OMAP2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * @st_offset: reset status register offset, not used for OMAP2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * Some IPs like dsp or iva contain processors that require an HW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * reset line to be asserted / deasserted in order to fully enable the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * IP. These modules may have multiple hard-reset lines that reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * different 'submodules' inside the IP block. This function will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * take the submodule out of reset and wait until the PRCM indicates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * that the reset has completed before returning. Returns 0 upon success or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * -EINVAL upon an argument error, -EEXIST if the submodule was already out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * of reset, or -EBUSY if the submodule did not exit reset promptly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int omap2_prm_deassert_hardreset(u8 rst_shift, u8 st_shift, u8 part,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) s16 prm_mod, u16 rst_offset, u16 st_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 rst, st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) rst = 1 << rst_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) st = 1 << st_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Check the current status to avoid de-asserting the line twice */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, rst) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return -EEXIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Clear the reset status by writing 1 to the status bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) omap2_prm_rmw_mod_reg_bits(0xffffffff, st, prm_mod, OMAP2_RM_RSTST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* de-assert the reset control line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) omap2_prm_rmw_mod_reg_bits(rst, 0, prm_mod, OMAP2_RM_RSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* wait the status to be set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) omap_test_timeout(omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) st),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MAX_MODULE_HARDRESET_WAIT, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Powerdomain low-level functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Common functions across OMAP2 and OMAP3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u8 pwrst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) OMAP2_PM_PWSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u8 pwrst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) OMAP2_PM_PWSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) OMAP2_PM_PWSTCTRL, m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) v = pwrst << __ffs(OMAP_LOGICRETSTATE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) omap2_prm_rmw_mod_reg_bits(OMAP_LOGICRETSTATE_MASK, v, pwrdm->prcm_offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) OMAP2_PM_PWSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u32 c = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * REVISIT: pwrdm_wait_transition() may be better implemented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * via a callback and a periodic timer check -- how long do we expect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * powerdomain transitions to take?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* XXX Is this udelay() value meaningful? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs, OMAP2_PM_PWSTST) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) OMAP_INTRANSITION_MASK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) (c++ < PWRDM_TRANSITION_BAILOUT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (c > PWRDM_TRANSITION_BAILOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) pr_err("powerdomain: %s: waited too long to complete transition\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) pwrdm->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) pr_debug("powerdomain: completed transition in %d loops\n", c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct clockdomain *clkdm2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct clockdomain *clkdm2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct clockdomain *clkdm2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PM_WKDEP, (1 << clkdm2->dep_bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* XXX Caller must hold the clkdm's powerdomain lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct clkdm_dep *cd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u32 mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (!cd->clkdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) continue; /* only happens if data is erroneous */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* PRM accesses are slow, so minimize them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) mask |= 1 << cd->clkdm->dep_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) cd->wkdep_usecount = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PM_WKDEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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