^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP2xxx Power/Reset Management (PRM) register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2008-2010 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Paul Walmsley
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * The PRM hardware modules on the OMAP2/3 are quite similar to each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * other. The PRM on OMAP4 has a new register layout, and is handled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * in a separate file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef __ARCH_ARM_MACH_OMAP2_PRM2XXX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define __ARCH_ARM_MACH_OMAP2_PRM2XXX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "prcm-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "prm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "prm2xxx_3xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define OMAP2420_PRM_REGADDR(module, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define OMAP2430_PRM_REGADDR(module, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * OMAP2-specific global PRM registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Use {read,write}l_relaxed() with these registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * With a few exceptions, these are the register names beginning with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * PRCM_* on 24xx. (The exceptions are the IRQSTATUS and IRQENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * bits.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OMAP2_PRCM_REVISION_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OMAP2420_PRCM_REVISION OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OMAP2_PRCM_SYSCONFIG_OFFSET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OMAP2420_PRCM_SYSCONFIG OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OMAP2420_PRCM_IRQSTATUS_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OMAP2420_PRCM_IRQENABLE_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OMAP2_PRCM_VOLTCTRL_OFFSET 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OMAP2420_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OMAP2_PRCM_VOLTST_OFFSET 0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OMAP2420_PRCM_VOLTST OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OMAP2_PRCM_CLKSRC_CTRL_OFFSET 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OMAP2420_PRCM_CLKSRC_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OMAP2_PRCM_CLKOUT_CTRL_OFFSET 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OMAP2420_PRCM_CLKOUT_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET 0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OMAP2420_PRCM_CLKEMUL_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OMAP2_PRCM_CLKCFG_CTRL_OFFSET 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OMAP2420_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OMAP2420_PRCM_CLKCFG_STATUS OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OMAP2_PRCM_VOLTSETUP_OFFSET 0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OMAP2420_PRCM_VOLTSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OMAP2_PRCM_CLKSSETUP_OFFSET 0x0094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OMAP2420_PRCM_CLKSSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OMAP2_PRCM_POLCTRL_OFFSET 0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OMAP2420_PRCM_POLCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OMAP2430_PRCM_REVISION OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OMAP2430_PRCM_SYSCONFIG OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OMAP2430_PRCM_IRQSTATUS_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OMAP2430_PRCM_IRQENABLE_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OMAP2430_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OMAP2430_PRCM_VOLTST OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OMAP2430_PRCM_CLKSRC_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OMAP2430_PRCM_CLKOUT_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OMAP2430_PRCM_CLKEMUL_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define OMAP2430_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OMAP2430_PRCM_CLKCFG_STATUS OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OMAP2430_PRCM_VOLTSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OMAP2430_PRCM_CLKSSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OMAP2430_PRCM_POLCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * Module specific PRM register offsets from PRM_BASE + domain offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * Use prm_{read,write}_mod_reg() with these registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * With a few exceptions, these are the register names beginning with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * {PM,RM}_* on both OMAP2/3 SoC families.. (The exceptions are the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * IRQSTATUS and IRQENABLE bits.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Register offsets appearing on both OMAP2 and OMAP3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define OMAP2_RM_RSTCTRL 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define OMAP2_RM_RSTTIME 0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OMAP2_RM_RSTST 0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define OMAP2_PM_PWSTCTRL 0x00e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define OMAP2_PM_PWSTST 0x00e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PM_WKEN 0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PM_WKEN1 PM_WKEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PM_WKST 0x00b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PM_WKST1 PM_WKST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PM_WKDEP 0x00c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PM_EVGENCTRL 0x00d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PM_EVGENONTIM 0x00d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PM_EVGENOFFTIM 0x00dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* OMAP2xxx specific register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define OMAP24XX_PM_WKEN2 0x00a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define OMAP24XX_PM_WKST2 0x00b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #ifndef __ASSEMBLER__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Function prototypes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) extern int omap2xxx_clkdm_sleep(struct clockdomain *clkdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int __init omap2xxx_prm_init(const struct omap_prcm_init_data *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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