^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP2/3/4 Power/Reset Management (PRM) bitfield definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2010 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Paul Walmsley
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __ARCH_ARM_MACH_OMAP2_PRM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "prcm-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) # ifndef __ASSEMBLER__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) extern struct omap_domain_base prm_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) extern u16 prm_features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) extern void omap2_set_globals_prm(void __iomem *prm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) int omap_prcm_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) int omap2_prm_base_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) int omap2_prcm_base_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) # endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * prm_features flag values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * PRM_HAS_IO_WAKEUP: has IO wakeup capability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * PRM_HAS_VOLTAGE: has voltage domains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PRM_HAS_IO_WAKEUP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PRM_HAS_VOLTAGE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * MAX_MODULE_SOFTRESET_WAIT: Maximum microseconds to wait for OMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * module to softreset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MAX_MODULE_SOFTRESET_WAIT 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * submodule to exit hardreset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MAX_MODULE_HARDRESET_WAIT 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * Register bitfields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * 2430: PM_PWSTST_MDM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * PM_PWSTST_NEON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OMAP_INTRANSITION_MASK (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * 2430: PM_PWSTST_MDM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * PM_PWSTST_NEON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OMAP_POWERSTATEST_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OMAP_POWERSTATEST_MASK (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * PM_PWSTCTRL_DSP, PM_PWSTST_MPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * 2430: PM_PWSTCTRL_MDM shared bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * PM_PWSTCTRL_NEON shared bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OMAP_POWERSTATE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OMAP_POWERSTATE_MASK (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * Standardized OMAP reset source bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * To the extent these happen to match the hardware register bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * shifts, it's purely coincidental. Used by omap-wdt.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * OMAP_UNKNOWN_RST_SRC_ID_SHIFT is a special value, used whenever
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * there are any bits remaining in the global PRM_RSTST register that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * haven't been identified, or when the PRM code for the current SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * doesn't know how to interpret the register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define OMAP_SECU_VIOL_RST_SRC_ID_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define OMAP_MPU_WD_RST_SRC_ID_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define OMAP_SECU_WD_RST_SRC_ID_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define OMAP_EXTWARM_RST_SRC_ID_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define OMAP_VDD_IVA_VM_RST_SRC_ID_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define OMAP_ICEPICK_RST_SRC_ID_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define OMAP_ICECRUSHER_RST_SRC_ID_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define OMAP_C2C_RST_SRC_ID_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define OMAP_UNKNOWN_RST_SRC_ID_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #ifndef __ASSEMBLER__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * struct prm_reset_src_map - map register bitshifts to standard bitshifts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @reg_shift: bitshift in the PRM reset source register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * @std_shift: bitshift equivalent in the standard reset source list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * The fields are signed because -1 is used as a terminator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct prm_reset_src_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) s8 reg_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) s8 std_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * struct prm_ll_data - fn ptrs to per-SoC PRM function implementations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * @read_reset_sources: ptr to the SoC PRM-specific get_reset_source impl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * @was_any_context_lost_old: ptr to the SoC PRM context loss test fn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * @clear_context_loss_flags_old: ptr to the SoC PRM context loss flag clear fn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * @late_init: ptr to the late init function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * @assert_hardreset: ptr to the SoC PRM hardreset assert impl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * @deassert_hardreset: ptr to the SoC PRM hardreset deassert impl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * XXX @was_any_context_lost_old and @clear_context_loss_flags_old are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * deprecated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct prm_ll_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 (*read_reset_sources)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) bool (*was_any_context_lost_old)(u8 part, s16 inst, u16 idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) void (*clear_context_loss_flags_old)(u8 part, s16 inst, u16 idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int (*late_init)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int (*assert_hardreset)(u8 shift, u8 part, s16 prm_mod, u16 offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int (*deassert_hardreset)(u8 shift, u8 st_shift, u8 part, s16 prm_mod,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u16 offset, u16 st_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int (*is_hardreset_asserted)(u8 shift, u8 part, s16 prm_mod,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u16 offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) void (*reset_system)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int (*clear_mod_irqs)(s16 module, u8 regs, u32 wkst_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 (*vp_check_txdone)(u8 vp_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) void (*vp_clear_txdone)(u8 vp_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) extern int prm_register(struct prm_ll_data *pld);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) extern int prm_unregister(struct prm_ll_data *pld);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int omap_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod, u16 offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int omap_prm_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 prm_mod,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u16 offset, u16 st_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int omap_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) extern u32 prm_read_reset_sources(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) extern bool prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) extern void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) void omap_prm_reset_system(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) void omap_prm_reconfigure_io_chain(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int omap_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * Voltage Processor (VP) identifiers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define OMAP3_VP_VDD_MPU_ID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define OMAP3_VP_VDD_CORE_ID 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define OMAP4_VP_VDD_CORE_ID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define OMAP4_VP_VDD_IVA_ID 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define OMAP4_VP_VDD_MPU_ID 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 omap_prm_vp_check_txdone(u8 vp_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) void omap_prm_vp_clear_txdone(u8 vp_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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