^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP44xx Power Management register bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009-2010 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2009-2010 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Paul Walmsley (paul@pwsan.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Rajendra Nayak (rnayak@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Benoit Cousson (b-cousson@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * This file is automatically generated from the OMAP hardware databases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * We respectfully ask that any modifications to this file be coordinated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * with the public linux-omap@vger.kernel.org mailing list and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * authors above to ensure that the autogeneration scripts are kept
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * up-to-date with the file contents.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define OMAP4430_C2C_RST_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define OMAP4430_CMDRA_VDD_CORE_L_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define OMAP4430_CMDRA_VDD_IVA_L_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define OMAP4430_CMDRA_VDD_MPU_L_MASK (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define OMAP4430_DATA_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define OMAP4430_ERRORGAIN_MASK (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define OMAP4430_ERROROFFSET_MASK (0xff << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define OMAP4430_EXTERNAL_WARM_RST_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define OMAP4430_FORCEUPDATE_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OMAP4430_GLOBAL_COLD_RST_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OMAP4430_GLOBAL_WUEN_MASK (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OMAP4430_HSMCODE_MASK (0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OMAP4430_SRMODEEN_MASK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OMAP4430_HSMODEEN_MASK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OMAP4430_HSSCLL_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OMAP4430_ICEPICK_RST_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OMAP4430_INITVDD_MASK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define OMAP4430_INITVOLTAGE_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OMAP4430_LASTPOWERSTATEENTERED_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OMAP4430_LASTPOWERSTATEENTERED_MASK (0x3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OMAP4430_LOGICRETSTATE_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OMAP4430_LOGICRETSTATE_MASK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OMAP4430_LOGICSTATEST_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OMAP4430_LOGICSTATEST_MASK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OMAP4430_LOSTCONTEXT_DFF_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OMAP4430_LOSTMEM_AESSMEM_MASK (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OMAP4430_LOWPOWERSTATECHANGE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OMAP4430_LOWPOWERSTATECHANGE_MASK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OMAP4430_MPU_WDT_RST_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OMAP4430_OCP_NRET_BANK_STATEST_MASK (0x3 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OMAP4430_OFF_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OMAP4430_ON_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OMAP4430_ON_MASK (0xff << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OMAP4430_ONLP_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OMAP4430_RAMP_DOWN_COUNT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OMAP4430_RAMP_UP_COUNT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OMAP4430_RAMP_UP_PRESCAL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OMAP4430_REGADDR_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OMAP4430_RET_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OMAP4430_RST_GLOBAL_WARM_SW_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OMAP4430_SA_VDD_CORE_L_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OMAP4430_SA_VDD_CORE_L_0_6_MASK (0x7f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OMAP4430_SA_VDD_IVA_L_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK (0x7f << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OMAP4430_SA_VDD_MPU_L_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK (0x7f << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OMAP4430_SCLH_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OMAP4430_SCLL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OMAP4430_SECURE_WDT_RST_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OMAP4430_SLAVEADDR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OMAP4430_SMPSWAITTIMEMAX_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define OMAP4430_SMPSWAITTIMEMIN_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OMAP4430_TIMEOUT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OMAP4430_TIMEOUTEN_MASK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OMAP4430_VALID_MASK (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OMAP4430_VDDMAX_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OMAP4430_VDDMIN_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OMAP4430_VOLRA_VDD_CORE_L_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define OMAP4430_VOLRA_VDD_IVA_L_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define OMAP4430_VOLRA_VDD_MPU_L_MASK (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define OMAP4430_VPENABLE_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define OMAP4430_VPVOLTAGE_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define OMAP4430_VP_CORE_TRANXDONE_ST_MASK (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define OMAP4430_VP_IVA_TRANXDONE_ST_MASK (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define OMAP4430_VP_MPU_TRANXDONE_ST_MASK (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define OMAP4430_VSTEPMAX_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define OMAP4430_VSTEPMIN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define OMAP4430_WUCLK_CTRL_MASK (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OMAP4430_WUCLK_STATUS_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define OMAP4430_WUCLK_STATUS_MASK (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags