Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  * AM33XX PRM_XXX register bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "prm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AM33XX_GFX_MEM_ONSTATE_MASK			(0x3 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AM33XX_GFX_MEM_RETSTATE_MASK			(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AM33XX_GFX_MEM_STATEST_MASK			(0x3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AM33XX_GLOBAL_WARM_SW_RST_MASK			(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AM33XX_RST_GLOBAL_WARM_SW_MASK			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AM33XX_PRUSS_MEM_ONSTATE_MASK			(0x3 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AM33XX_PRUSS_MEM_RETSTATE_MASK			(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AM33XX_PRUSS_MEM_STATEST_MASK			(0x3 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AM33XX_LASTPOWERSTATEENTERED_SHIFT		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AM33XX_LASTPOWERSTATEENTERED_MASK		(0x3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AM33XX_LOGICRETSTATE_MASK			(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AM33XX_LOGICRETSTATE_3_3_MASK			(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AM33XX_LOGICSTATEST_SHIFT			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AM33XX_LOGICSTATEST_MASK			(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AM33XX_LOWPOWERSTATECHANGE_SHIFT		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AM33XX_LOWPOWERSTATECHANGE_MASK			(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AM33XX_MPU_L1_ONSTATE_MASK			(0x3 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AM33XX_MPU_L1_RETSTATE_MASK			(1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AM33XX_MPU_L1_STATEST_MASK			(0x3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AM33XX_MPU_L2_ONSTATE_MASK			(0x3 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AM33XX_MPU_L2_RETSTATE_MASK			(1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AM33XX_MPU_L2_STATEST_MASK			(0x3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AM33XX_MPU_RAM_ONSTATE_MASK			(0x3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AM33XX_MPU_RAM_RETSTATE_MASK			(1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AM33XX_MPU_RAM_STATEST_MASK			(0x3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AM33XX_PER_MEM_ONSTATE_MASK			(0x3 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AM33XX_PER_MEM_RETSTATE_MASK			(1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AM33XX_PER_MEM_STATEST_MASK			(0x3 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AM33XX_RAM_MEM_ONSTATE_MASK			(0x3 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AM33XX_RAM_MEM_RETSTATE_MASK			(1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AM33XX_RAM_MEM_STATEST_MASK			(0x3 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #endif