Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * DRA7xx PRCM MPU instance offset macros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Generated by code originally written by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Paul Walmsley (paul@pwsan.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * Rajendra Nayak (rnayak@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  * Benoit Cousson (b-cousson@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  * This file is automatically generated from the OMAP hardware databases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  * We respectfully ask that any modifications to this file be coordinated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * with the public linux-omap@vger.kernel.org mailing list and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * authors above to ensure that the autogeneration scripts are kept
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * up-to-date with the file contents.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU7XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU7XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "prcm_mpu_44xx_54xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DRA7XX_PRCM_MPU_BASE			0x48243000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DRA7XX_PRCM_MPU_REGADDR(inst, reg)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	OMAP2_L4_IO_ADDRESS(DRA7XX_PRCM_MPU_BASE + (inst) + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* MPU_PRCM instances */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DRA7XX_MPU_PRCM_OCP_SOCKET_INST	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DRA7XX_MPU_PRCM_DEVICE_INST	0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DRA7XX_MPU_PRCM_PRM_C0_INST	0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DRA7XX_MPU_PRCM_CM_C0_INST	0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DRA7XX_MPU_PRCM_PRM_C1_INST	0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DRA7XX_MPU_PRCM_CM_C1_INST	0x0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* PRCM_MPU clockdomain register offsets (from instance start) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* MPU_PRCM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* MPU_PRCM.PRCM_MPU_OCP_SOCKET register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DRA7XX_REVISION_PRCM_MPU_OFFSET				0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* MPU_PRCM.PRCM_MPU_DEVICE register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DRA7XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET		0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DRA7XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET	0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* MPU_PRCM.PRCM_MPU_PRM_C0 register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DRA7XX_PM_CPU0_PWRSTCTRL_OFFSET				0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DRA7XX_PM_CPU0_PWRSTST_OFFSET				0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DRA7XX_RM_CPU0_CPU0_RSTCTRL_OFFSET			0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DRA7XX_RM_CPU0_CPU0_RSTST_OFFSET			0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DRA7XX_RM_CPU0_CPU0_CONTEXT_OFFSET			0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* MPU_PRCM.PRCM_MPU_CM_C0 register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DRA7XX_CM_CPU0_CLKSTCTRL_OFFSET				0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DRA7XX_CM_CPU0_CPU0_CLKCTRL_OFFSET			0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DRA7XX_CM_CPU0_CPU0_CLKCTRL				DRA7XX_MPU_PRCM_REGADDR(DRA7XX_MPU_PRCM_CM_C0_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* MPU_PRCM.PRCM_MPU_PRM_C1 register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DRA7XX_PM_CPU1_PWRSTCTRL_OFFSET				0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DRA7XX_PM_CPU1_PWRSTST_OFFSET				0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DRA7XX_RM_CPU1_CPU1_RSTCTRL_OFFSET			0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DRA7XX_RM_CPU1_CPU1_RSTST_OFFSET			0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DRA7XX_RM_CPU1_CPU1_CONTEXT_OFFSET			0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* MPU_PRCM.PRCM_MPU_CM_C1 register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DRA7XX_CM_CPU1_CLKSTCTRL_OFFSET				0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DRA7XX_CM_CPU1_CPU1_CLKCTRL_OFFSET			0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DRA7XX_CM_CPU1_CPU1_CLKCTRL				DRA7XX_MPU_PRCM_REGADDR(DRA7XX_MPU_PRCM_CM_C1_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #endif